COM20022I Ver la hoja de datos (PDF) - SMSC -> Microchip
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Lista de partido
COM20022I Datasheet PDF : 88 Pages
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A0-A2
nCS
nRD
nWR
D0-D15
t1
Note 3 t3
t10
t11
VALID
t2
t4
t8
t9
t5
t5**
Note 2
t6
t7
t12
VALID DATA
nIOCS16
VALID VALUE
CASE 2: BUSTMG pin = LOW
Parameter
min
max units
t1 Address Setup to nWR Active
0
nS
t2 Address Hold from nWR Inactive
t3 nCS Setup to WR Active
0
nS
0
nS
t4 nCS Hold from nWR Inactive
t5 Cycle Time (nWR to Next )**
t6 Valid Data Setup to nWR High
t7 Data Hold from nWR High
t8 nWR Low Width
t9 nWR High Width
t10 nRD to nWR Low
t11 nIOCS16 Output Delay from nCS Low
t12 nIOCS16 Hold Delay from nCS High
0
4TARB*
30
10
65
30
20
0*****
nS
nS
nS
nS
nS
nS
nS
40**** nS
nS
* TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
**** t11 is measured from the latest active (valid) timing among nCS, A0-A2.
***** t12 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.
Note 1:
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
** Note 2: Any cycle occurring after a write to Address Pointer Low Register requires a
minimum of 4TARB from the trailing edge of nWR to the leading edge of the
next nWR.
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Note 3: +
!"#
+&
' *(( ) &
FIGURE 22B - NON-MULTIPLEXED BUS, 80XX-LIKE
CONTROL SIGNALS; WRITE CYCLE
71
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