FDC37C666GT(1994) Ver la hoja de datos (PDF) - SMSC -> Microchip

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FDC37C666GT
(Rev.:1994)

High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers

SMSC -> Microchip 

PIN NO.

NAME

22 IDE Data Bit 7

58 Power Good

DESCRIPTION OF PIN FUNCTIONS

BUFFER

SYMBOL TYPE

DESCRIPTION

IDED7

I/O24

IDE data bit 7 in the AT mode. IDED7

transfers data at I/O addresses 1F0H-1F7H

(R/W), 3F6 (R/W), 3F7(W). IDED7 should

be connected to IDE data bit 7. The

FDC37C665GT functions as a buffer

transferring data bit 7 between the IDE

device and the host. During I/O read of

3F7H, IDED7 is the FDC disk change bit. In

the XT mode, IDE7 is not used.

MISCELLANEOUS

PWRGD

I

FDC37C665GT (Motherboard Mode): This

input indicates that the power (VCC) is valid.

For device operation, PWRGD must be

active. When PWRGD is inactive, all inputs

to the FDC37C665GT are disconnected and

put in a low power mode, all outputs are put

into high impedance. The contents of all

registers are preserved as long as VCC has a

valid value. The driver current drain in this

mode drops to ISTBY - standby current.

This input has a weak pullup resistor to VCC.

nGame Port

Chip Select

20 CLOCK 1

21 CLOCK 2

nGAMECS

PADCF

X1/CLK1

X2/CLK2

O4 FDC37C666GT (Adapter Mode): This is the

Game Port Chip Select output - active low.

It will go active when the I/O address is

201H.

I

ICLK

OCLK

17

FDC37C666GT (Adapter Mode): Parallel

Port Mode Control. Refer to FDC37C666GT

hardware configuration for more

information. Read and latched during reset

active.

The external connection for a parallel

resonant 24 MHz crystal. A CMOS

compatible oscillator is required if crystal is

not used.

24 MHz crystal. If an external clock is used,

this pin should not be connected. This pin

should not be used to drive any other

drivers.

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