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FDC37C665GT

High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers

SMSC -> Microchip 

PIN NO.

NAME

DESCRIPTION OF PIN FUNCTIONS

BUFFER

SYMBOL TYPE

DESCRIPTION

HOST PROCESSOR INTERFACE

48-51 Data Bus 0-7

53-56

D0-D7

I/O24

The data bus connection used by the host

microprocessor to transmit data to and from

the FDC37C665GT. These pins are in a

high-impedance state when not in the output

mode.

44 nI/O Read

nIOR

I

This active low signal is issued by the host

microprocessor to indicate a read operation.

45 nI/O Write

nIOW

I

This active low signal is issued by the host

microprocessor to indicate a write operation.

46 Address Enable AEN

I

Active high Address Enable indicates DMA

operations on the host data bus. Used

internally to qualify appropriate address

decodes.

28-34 I/O Address

41-43

A0-A9

I

These host address bits determine the I/O

address to be accessed during nIOR and

nIOW cycles. These bits are latched

internally by the leading edge of nIOR and

nIOW.

52 FDC DMA

Request

FDRQ

O24 This active high output is the DMA request

for byte transfers of data to the host. This

signal is cleared on the last byte of the data

transfer by the nDACK signal going low (or

by nIOR going low if nDACK was already

low as in demand mode).

36 nDMA Acknowle- nDACK

dge

I

An active low input acknowledging the

request for a DMA transfer of data. This

input enables the DMA read or write

internally.

35 Terminal Count TC

I

This signal indicates to the FDC37C665GT

that data transfer is complete. TC is only

accepted when nDACK or nPDACK is low.

In AT and PS/2 model 30 modes, TC is

active high and in PS/2 mode, TC is active

low.

5

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