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1032

In-System Programmable High Density PLD

Lattice Semiconductor 

Specifications ispLSI 1032/883

External Timing Parameters

Over Recommended Operating Conditions

PARAMETER

TEST 5

COND.

#2

DESCRIPTION1

tpd1

tpd2

fmax (Int.)

fmax (Ext.)

fmax (Tog.)

tsu1

tco1

th1

tsu2

tco2

th2

tr1

trw1

ten

tdis

twh

twl

tsu5

th5

A 1 Data Propagation Delay, 4PT bypass, ORP bypass

A 2 Data Propagation Delay, Worst Case Path

A 3 Clock Frequency with Internal Feedback3

–

4

Clock

Frequency

with

External

Feedback(tsu2

1

+

) tco1

– 5 Clock Frequency, Max Toggle4

– 6 GLB Reg. Setup Time before Clock, 4PT bypass

A 7 GLB Reg. Clock to Output Delay, ORP bypass

– 8 GLB Reg. Hold Time after Clock, 4 PT bypass

– 9 GLB Reg. Setup Time before Clock

– 10 GLB Reg. Clock to Output Delay

– 11 GLB Reg. Hold Time after Clock

A 12 Ext. Reset Pin to Output Delay

– 13 Ext. Reset Pulse Duration

B 14 Input to Output Enable

C 15 Input to Output Disable

– 16 Ext. Sync. Clock Pulse Duration, High

– 17 Ext. Sync. Clock Pulse Duration, Low

– 18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)

– 19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)

1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-Bit counter using GRP feedback.

4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.

5. Reference Switching Test Conditions section.

-60

UNITS

MIN. MAX.

– 20 ns

– 25 ns

60 – MHz

38 – MHz

83 – MHz

9 – ns

– 13 ns

0 – ns

13 – ns

– 16 ns

0 – ns

– 22.5 ns

13 – ns

– 24 ns

– 24 ns

6 – ns

6 – ns

2.5 – ns

8.5 – ns

Table 2-0030-32/60C

5

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