SN74LS138N(1999) Ver la hoja de datos (PDF) - ON Semiconductor

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SN74LS138N
(Rev.:1999)

1-of-8 Decoder/Demultiplexer

ON Semiconductor 

SN74LS138

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC O0 O1 O2 O3 O4 O5 O6

16 15 14 13 12 11 10 9

NOTE:

The Flatpak version has the same

pinouts (Connection Diagram) as

the Dual In-Line Package.

1 2 3 4 56 78

A0 A1 A2 E1 E2 E3 O7 GND

PIN NAMES

A0 – A2

E1, E2

E3

O0 – O7

Address Inputs

Enable (Active LOW) Inputs

Enable (Active HIGH) Input

Active LOW Outputs

LOADING (Note a)

HIGH

LOW

0.5 U.L.

0.5 U.L.

0.5 U.L.

10 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

5 U.L.

NOTES:

a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

LOGIC SYMBOL

123

456

1 23

A0 A1 A2

E

O0 O1 O2 O3 O4 O5 O6 O7

15 14 13 12 11 10 9 7

VCC = PIN 16

GND = PIN 8

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