74F251A Ver la hoja de datos (PDF) - Fairchild Semiconductor
Número de pieza
componentes Descripción
Lista de partido
74F251A Datasheet PDF : 7 Pages
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Unit Loading/Fan Out
Pin Names
Description
S0–S2
OE
I0–I7
Z
Z
Select Inputs
3-STATE Output Enable Input (Active LOW)
Multiplexer Inputs
3-STATE Multiplexer Output
Complementary 3-STATE Multiplexer Output
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
150/40 (33.3)
150/40 (33.3)
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−3 mA/24 mA (20 mA)
−3 mA/24 mA (20 mA)
Functional Description
Truth Table
This device is a logical implementation of a single-pole, 8-
position switch with the switch position controlled by the
Inputs
Outputs
state of three Select inputs, S0, S1, S2. Both assertion and
OE
S2
S1
S0
Z
Z
negation outputs are provided. The Output Enable input
(OE) is active LOW. When it is activated, the logic function
provided at the output is:
H
X
X
L
L
L
X
Z
Z
L
I0
I0
Z = OE •(I0•S0•S1 •S2 + I1•S0•S 1•S2 +
I2•S0•S1•S2 + I3•S0•S1•S2 +
L
L
L
H
I1
I1
L
L
H
L
I2
I2
I4•S0•S1•S2 + I5•S0•S1•S2 +
I6•S0•S1•S2 + I7•S0•S1•S2)
When the Output Enable is HIGH, both outputs are in the
high impedance (High Z) state. This feature allows multi-
L
L
H
H
I3
I3
L
H
L
L
I4
I4
L
H
L
H
I5
I5
plexer expansion by tying the outputs of up to 128 devices
L
H
H
L
I6
I6
together. When the outputs of the 3-STATE devices are
L
H
H
H
I7
I7
tied together, all but one device must be in the high imped- H = HIGH Voltage Level
ance state to avoid high currents that would exceed the L = LOW Voltage Level
maximum ratings. The Output Enable signals should be X = Immaterial
designed to ensure there is no overlap in the active LOW Z = High Impedance
portion of the enable voltages.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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