AD1816 Ver la hoja de datos (PDF) - Analog Devices
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AD1816 Datasheet PDF : 52 Pages
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AD1816A
TIMING PARAMETERS (Guaranteed Over Operating Temperature Range)
Parameter
IOW/IOR Strobe Width
IOW/IOR Rising to IOW/IOR Falling
Write Data Setup to IOW Rising
IOW Falling to Valid Read Data
AEN Setup to IOW/IOR Falling
AEN Hold from IOW/IOR Rising
Adr Setup to IOW/IOR Falling
Adr Hold from IOW/IOR Rising
DACK Rising to IOW/IOR Falling
Data Hold from IOR Rising
Data Hold from IOW Rising
DRQ Hold from IOW/IOR Falling
DACK Hold from IOW/IOR Rising
Data [SDI] Input Setup Time to SCLK*
Data [SDI] Input Hold Time from SCLK*
Frame Sync [SDFS] HI Pulse Width*
Clock [SCLK] to Frame Sync [SDFS]
Propagation Delay*
Clock [SCLK] to Output Data [SDO] Valid*
RESET Pulse Width
BCLK HI Pulse Width
BCLK LO Pulse Width
BCLK Period
LRCLK Setup
SDATA Setup
SDATA Hold
Symbol
tSTW
tBWDN
tWDSU
tRDDV
tAESU
tAEHD
tADSU
tADHD
tDKSU
tDHD1
tDHD2
tDRHD
tDKHD
tS
tH
tFSW
tPD
tDV
tRPWL
tDBH
tDBL
tDBP
tDLS
tDDS
tDDH
Min
Typ
Max
100
80
10
40
10
0
10
0
20
2
15
25
10
15
10
80
15
15
100
25
25
50
5
5
5
NOTES
*Guaranteed, not tested.
†All ISA pins MIDI_OUT IOL = 24 mA. Refer to pin description for individual output drive levels.
Specifications subject to change without notice.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DRQ (0, 1, 3)
DACK (0, 1, 3)
AEN
IOR
PC_D [7:0]
PC_A [15:0]
tDKSU
tAESU
tSTW
tRDDV
tADSU
tDKHD
tAEHD
tDHD1
tADHD
Figure 1. PIO Read Cycle
DRQ (0, 1, 3)
DACK (0, 1, 3)
AEN
IOW
PC_D [7:0]
PC_A [15:0]
tDKSU
tAESU
tDKHD
tAEHD
tADSU
tSTW
tWDSU
tDHD2
tADHD
Figure 2. PIO Write Cycle
–6–
REV. A
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