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AT26DF161

16-megabit 2.7-volt Only Serial Firmware DataFlash® Memory

Atmel Corporation 

Figure 2-1. 8-SOIC Top View

3. Block Diagram

CS 1

SO 2

WP 3

GND 4

8 VCC

7 NC

6 SCK

5 SI

AT26DF161

Figure 2-2. 8-MLF Top View

CS 1

SO 2

WP 3

GND 4

8 VCC

7 NC

6 SCK

5 SI

CONTROL AND

CS

PROTECTION LOGIC

SCK

SI

SO

INTERFACE

CONTROL

AND

LOGIC

Y-DECODER

WP

X-DECODER

I/O BUFFERS

AND LATCHES

SRAM

DATA BUFFER

Y-GATING

FLASH

MEMORY

ARRAY

4. Memory Array

To provide the greatest flexibility, the memory array of the AT26DF161 can be erased in four lev-

els of granularity including a full chip erase. In addition, the array has been divided into physical

sectors of uniform size, of which each sector can be individually protected from program and

erase operations. The size of the physical sectors is optimized for both code and data storage

applications, allowing both code and data segments to reside in their own isolated

regions. Figure 4-1 on page 4 illustrates the breakdown of each erase level as well as the break-

down of each physical sector.

3

3599F–DFLASH–09/06

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