GS88219AB-250 Ver la hoja de datos (PDF) - Giga Semiconductor

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GS88219AB-250

512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs

Giga Semiconductor 

Datasheet Errata

Revision: 5/17/02

GS88219/37AB

GS88219/37A BGA Pin Description

Pin Location

Symbol Type

P4, N4

A0, A1

I

A2, A3, A5, A6, B3, B5, C2, C3, C5,

C6, R2, R6, T3, T5

An

I

T4

An

I

T2, T6

NC

—

T2, T6

An

I

K7, L7, N7, P7, K6, L6, M6, N6, P6 DQA1–DQA9

H7, G7, E7, D7, H6, G6, F6, E6, D6 DQB1–DQB9

H1, G1, E1, D1, H2, G2, F2, E2, D2 DQC1–DQC9

I/O

K1, L1, N1, P1, K2, L2, M2, N2, P2 DQD1–DQD9

L5, G5, G3, L3

BA, BB, BC, BD I

P7, N6, L6, K7, H6, G7, F6, E7, D6 DQA1–DQA9

D1, E2, G2, H1, K2, L1, M2, N1, P2 DQB1–DQB9

I/O

L5, G3

BA, BB

I

B1, B2, C1, R1, T1, U6, B7, C7, J3,

J5

NC

—

P6, N7, M6, L7, K6, H7, G6, E6, D7,

D2, E1, F2, G1, H2, K1, L2, N2, P1,

NC

—

G5, L3, T4

K4

CK

I

M4

BW

I

H4

GW

I

E4

E1

I

F4

G

I

G4

ADV

I

A4, B4

ADSP, ADSC I

T7

ZZ

I

R3

LBO

I

L4

SCD

I

R7

PE

I

D4

ZQ

I

U2

TMS

I

Description

Address field LSBs and Address Counter Preset Inputs

Address Inputs

Address Input (x36 Versions)

No Connect (x36 Versions)

Address Input (x18 Version)

Data Input and Output pins (x36 Versions)

Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version)

Data Input and Output pins (x18 Version)

Byte Write Enable for DQA, DQB I/Os; active low (x18 Version)

No Connect

No Connect (x18 Version)

Clock Input Signal; active high

Byte Write—Writes all enabled bytes; active low

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

Output Enable; active low

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

Linear Burst Order mode; active low

Single Cycle Deselect/Dual Cycle Deselect Mode Control

Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)

FLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

Scan Test Mode Select

4/5

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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