GS882Z18AB-133 Ver la hoja de datos (PDF) - Giga Semiconductor

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GS882Z18AB-133

9Mb Pipelined and Flow Through Synchronous NBT SRAM

Giga Semiconductor 

CK

CKE

E

ADV

W

Bn

A0–An

DQ

G

GS882Z18/36AB/D-250/225/200/166/150/133

Flow Through Mode Timing

Write A

Write B

Write B+1 Read C

tKL

tKH

tKC

Cont

Read D

Write E

Read F

Write G

tH

tS

tH

tS

tH

tS

tH

tS

tH

tS

tH

tS

A

B

tH

tS

D(A)

D(B)

C

D

tKQ

tLZ

D(B+1)

Q(C)

tOHZ

E

F

G

tKQ

tKQX

tHZ

tLZ

Q(D)

D(E)

Q(F)

tOLZ

tOE

tKQX

D(G)

*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output

drivers are powered by VDDQ.

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.

Rev: 1.04 11/2004

21/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2001, GSI Technology

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