TDA9207 Ver la hoja de datos (PDF) - STMicroelectronics
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TDA9207 Datasheet PDF : 22 Pages
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TDA9207
3 - BLOCK DIAGRAM
TDA9207
IN1 1
VREF
Clamp
BLK
FBLK
24
12
Contrast
Output Clamp Pulse
(OCL)
Drive
VCCP
20
Output
Stage
21 OUT1
22 CO1/FB1
IN2 3
Green Channel
19 OUT2
15 CO2/FB2
IN3 5
ABL 2
GNDL 4
GNDA 6
VCCA 7
NC 8
BPCP
Blue Channel
17 OUT3
16 CO3/FB3
Contrast/8bit
Latches
Brightness Drive
8bits 3x8bits
Cut-off
8bits
18 GNDP
I2C
D/A
Bus
Decoder
Output
DC Level
IC
4bits
OSD
Cont.
4bits
VREF
23
14 13
HSYNC SDA SCL
or BPCP
9
10
11
OSD1 OSD2 OSD3
See Figure 12 for complete BPCP and OCL generation diagram
4 - FUNCTIONAL DESCRIPTION
4.1 RGB Input
The three RGB inputs have to be supplied through
coupling capacitors (100 nF).
The maximum input peak-to-peak video amplitude
is 1 V.
The input stage includes a clamping function. The
clamp uses the input serial capacitor as a ”memo-
ry capacitor”.
To avoid a discharge of the serial capacitor during
the line (due to leakage current), the input voltage
is referenced to the ground.
The clamp is gated by an internally generated
”Back Porch Clamping Pulse” (BPCP). Register 8
allows to choose the way to generate this BPCP
(see Figure 1).
When bit 0 is set to 0, the BPCP is synchronized
on the trailing or leading edge of HSYNC (Pin 23)
(bit 1 = 0: trailing edge, bit 1 = 1: leading edge).
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