CY7B9911V(1999) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7B9911V Datasheet PDF : 11 Pages
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CY7B9911V
3.3V RoboClock+
AC Test Loads and Waveforms
VCC
R1 R1=100
R2=100
CL = 30 pF
CL
R2 (Includes fixture and probe capacitance)
TTL AC Test Load
7B9911V–4
3.0V
2.0V
Vth =1.5V
0.8V
0.0V
≤1ns
TTL Input Test Waveform
2.0V
Vth =1.5V
0.8V
≤1ns
7B9911V–5
Switching Characteristics Over the Operating Range[2, 11]
CY7B9911V–5
Parameter
fNOM
Operating Clock
Frequency in MHz
Description
FS = LOW[1, 2]
FS = MID[1, 2]
FS = HIGH[1, 2 , 3]
Min.
15
25
40
Typ.
Max.
30
50
110
Unit
MHz
tRPWH
tRPWL
tU
tSKEWPR
tSKEW0
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tDEV
tPD
tODCV
tPWH
tPWL
tORISE
tOFALL
tLOCK
tJR
REF Pulse Width HIGH
5.0
ns
REF Pulse Width LOW
5.0
ns
Programmable Skew Unit
Zero Output Matched-Pair Skew (XQ0, XQ1)[13, 14]
Zero Output Skew (All Outputs)[13, 15]
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)[13, 17]
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)[13, 17]
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)[13, 17]
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)[13, 17]
Device-to-Device Skew[12, 18]
See Table 1
0.1
0.25
ns
0.25
0.5
ns
0.6
0.7
ns
0.5
1.0
ns
0.5
0.7
ns
0.5
1.0
ns
1.25
ns
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation[19]
Output HIGH Time Deviation from 50%[20]
Output LOW Time Deviation from 50%[20]
Output Rise Time[20, 21]
Output Fall Time[20, 21]
PLL Lock Time[22]
Cycle-to-Cycle Output
Jitter
RMS[12]
Peak-to-Peak[12]
– 0.5
0.0
+0.5
ns
– 1.0
0.0
+1.0
ns
2.5
ns
3
ns
0.15
1.0
1.5
ns
0.15
1.0
1.5
ns
0.5
ms
25
ps
200
ps
Notes:
11. Test measurement levels for the CY7B9911V are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2 ns or less and output loading as shown
in the AC Test Loads and Waveforms unless otherwise specified.
12. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are
loaded with 30 pF and terminated with 50Ω to VCC/2 (CY7B9911V).
14. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
15. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
16. CL=0 pF. For CL=30 pF, tSKEW0=0.35 ns.
17. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-
2 or Divide-by-4 mode).
18. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, etc.)
19. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
20. Specified with outputs loaded with 30 pF for the CY7B9911V–5 and –7 devices. Devices are terminated through 50Ω to VCC/2.tPWH is measured at 2.0V. tPWL is
measured at 0.8V.
21. tORISE and tOFALL measured between 0.8V and 2.0V.
22. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
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