CY7C008 Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C008 Datasheet PDF : 19 Pages
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Switching Characteristics Over the Operating Range[13] (continued)
Parameter
BUSY TIMING[19]
Description
tBLA
BUSY LOW from Address Match
tBHA
BUSY HIGH from Address Mismatch
tBLC
BUSY LOW from CE LOW
tBHC
BUSY HIGH from CE HIGH
tPS
Port Set-Up for Priority
tWB
R/W HIGH after BUSY (Slave)
tWH
R/W HIGH after BUSY HIGH (Slave)
tBDD[20]
BUSY HIGH to Data Valid
INTERRUPT TIMING[19]
tINS
INT Set Time
tINR
INT Reset Time
SEMAPHORE TIMING
tSOP
tSWRD
tSPS
tSAA
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
-12[1]
Min. Max.
12
12
12
12
5
0
11
12
12
12
10
5
5
12
CY7C008/009
CY7C018/019
-15
Min. Max.
15
15
15
15
5
0
13
15
15
15
10
5
5
15
CY7C008/009
CY7C018/019
-20
Min. Max. Unit
20
ns
20
ns
20
ns
17
ns
5
ns
0
ns
15
ns
20
ns
20
ns
20
ns
10
ns
5
ns
5
ns
20
ns
Data Retention Mode
The CY7C008/009 and CY7C018/019 are designed with
battery backup in mind. Data retention voltage and supply
current are guaranteed over temperature. The following rules
ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (4.5 volts).
Timing
VCC
CE
Data Retention Mode
4.5V
VCC > 2.0V
4.5V
tRC
VCC to VCC – 0.2V
VIH
Parameter
ICCDR1
Test Conditions[21]
@ VCCDR = 2V
Max.
1.5
Unit
mA
Notes:
19. Test conditions used are Load 1.
20. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
21. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
Document #: 38-06041 Rev. *D
Page 8 of 19
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