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CY7C1049DV33

4-Mbit (512 K × 8) Static RAM

Cypress Semiconductor 

CY7C1049DV33

Thermal Resistance

Tested initially and after any design or process changes that may affect these parameters.

Parameter

Description

JA

Thermal Resistance

(Junction to Ambient)

JC

Thermal Resistance

(Junction to Case)

Test Conditions

Still Air, soldered on a 3 × 4.5 inch, two layer printed

circuit board

36-pin SOJ

Package

57.91

36.73

44-pin TSOP II

Package Unit

50.66

C/W

17.17

C/W

AC Test Loads and Waveforms

Figure 1. AC Test Loads and Waveforms [4]

10 ns device

OUTPUT

Z = 50 

* CAPACITIVE LOAD CONSISTS

OF ALL COMPONENTS OF THE

TEST ENVIRONMENT

High Z characteristics:

50 

1.5 V

(a)

3.3 V

OUTPUT

5 pF

3.0 V

30 pF* GND

ALL INPUT PULSES

90%

90%

10%

10%

Rise Time: 1 V/ns

R 317

(b)

Fall Time: 1 V/ns

R2

351

(c)

Data Retention Characteristics

Over the Operating Range

Parameter

Description

Conditions [5]

Min

VDR

ICCDR

tCDR[3]

tR[6]

VCC for Data Retention

2.0

Data Retention Current

VCC = VDR = 2.0 V, CE > VCC – 0.3 V Industrial

–

VIN > VCC – 0.3 V or VIN < 0.3 V

Auto

–

Chip Deselect to Data Retention Time

0

Operation Recovery Time

tRC

Max Unit

–

V

10

mA

15

mA

–

ns

–

ns

Figure 2. Data Retention Waveform

DATA RETENTION MODE

VCC

3.0V

VDR > 2V

3.0V

tCDR

tR

CE

Notes

3. Tested initially and after any design or process changes that may affect these parameters.

4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 1 (a). High Z characteristics are tested for all speeds using the test load shown

in Figure 1 (c).

5. No input may exceed VCC + 0.3 V.

6. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s.

Document Number: 38-05475 Rev. *G

Page 5 of 14

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