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TMXF84622

155 Mbits/s/622 Mbits/s Interface SONET/SDH x84/x63 Ultramapper

Agere -> LSI Corporation 

Advance Data Sheet, Rev. 2

July 2001

TMXF84622 155 Mbits/s/622 Mbits/s Interface

SONET/SDH x84/x63 Ultramapper

Features (continued)

s DataLink (DS1-ESF DL) and SSM (E1 multiframe

Sa) fields read/writable.

s Supports all Ultramapper modes of operation.

s Complies with T1.107, T1.231, T1.403, G.703,

G.704, O.150.

System Test and Maintenance

s A variety of loopback modes implemented on

SONET/SDH side as well as on framer level.

s Built-in test pattern generator and monitor config-

urable for simultaneously testing E1, DS1, DS2, E3,

DS3, and STS1 (one channel each).

CDR Features

s Receives data at OC-12/STS-12 (622.08 Mbits/s)

data rate.

s Single low-voltage power supply.

s 155.52 MHz or 77.76 MHz input reference clock for

on-chip PLL.

s On-chip PLL for clock synthesis, requiring only one

external resistor, generating 16 phases, providing

resolution of ~100 ps.

s PLL bypass mode for functional test.

s Modular design to incorporate n = 2 to 16 channels.

s Meets type B jitter tolerance specification of ITU-T

Recommendation G.958.

s No output clock drift in absence of data transitions

once lock is acquired.

s Built-in test features.

Microprocessor Interface

s 21-bit address and 16-bit data interface with 16 MHz

to 66 MHz read and write access.

s Compatible with most industry-standard processors.

Chip Testing and Maintenance

s IEEE * 1149.1 JTAG boundary scan.

Interface to Other Agere Devices

Seamless interface to the following Agere Systems

devices:

s TADM042G5

s Super Mapper

Agere Systems Inc.

* IEEE is a registered trademark of the Institute of Electrical and

Electronics Engineers, Inc

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