GLT4116-45J4 Ver la hoja de datos (PDF) - G-Link Technology

Número de pieza

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GLT4116-45J4

64k x 16 CMOS Dynamic RAM with Fast Page Mode

G-Link Technology  

GLT41116

1

2

3

4

5

6

7

8

9

10

CLK

CKE

CE

ADV/LD

R/Wn

BWn

ADDRESS

A1

A2

A3

A4

A5

D/Q

WRITE D(A1)

READ Q(A2)

STALL

D (A1)

READ Q(A1)

Q (A2)

WRITE D(A2)

Q (A3)

STALL

NOP

D (A4)

READ Q(A3)

DESELECT

NOTE:

Don’t Care

1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE being used to create a “pause.” A WRITE is not performed during this cycle.

2. For this waveform, ZZ and OE are tied LOW.

3. CE represents three signals. When CE = 0, it represents CE = 0, CE2 = 0, CE2 = 1.

4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register.

Figure 3. NOP, STALL and DESELECT Timing

tKHQZ

tKHQX

D (A5)

Continue

DESELECT

Undefined

8

G-LINK Technology

July 1998 (Rev. 1)

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