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HB52RF648DC-75B Ver la hoja de datos (PDF) - Elpida Memory, Inc

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HB52RF648DC-75B Datasheet PDF : 20 Pages
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HB52RF648DC-B, HB52RD648DC-B
2 variations of burst sequence
Sequential
Interleave
Programmable CE latency: 2/3
Byte control by DQMB
Refresh cycles: 8192 refresh cycles/64 ms
2 variations of refresh
Auto refresh
Self refresh
Low self refresh current: HB52RF648DC-xxBL (L-version)
: HB52RD648DC-xxBL (L-version)
Ordering Information
Type No.
Frequency CE latency
HB52RF648DC-75B*1
HB52RF648DC-75BL*1
133 MHz 3
133 MHz 3
HB52RD648DC-A6B*1
HB52RD648DC-A6BL*1
HB52RD648DC-B6B*2
HB52RD648DC-B6BL*2
100 MHz 2/3
100 MHz 2/3
100 MHz 3
100 MHz 3
Notes: 1. 100 MHz operation at CE latency = 2.
2. 66 MHz operation at CE latency = 2.
Package
Contact pad
Small outline DIMM (144-pin) Gold
Data Sheet E0083H40
2

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