HFA3724 Ver la hoja de datos (PDF) - Intersil
Número de pieza
componentes Descripción
Lista de partido
HFA3724 Datasheet PDF : 24 Pages
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HFA3724
Pin Description (Continued)
PIN
SYMBOL
DESCRIPTION
63
LIM2_In-
Inverting input of Limiter amplifier 2.
64
LIM2_BYP- DC feedback pin for Limiter amplifier 2. Requires good decoupling and minimum wire length to a solid signal
ground.
65, 66,
67, 68,
69, 70,
71, 72,
73
GND
Ground. Connect to a solid ground plane.
74
LIM1_PE
Digital input control to enable the limiter amplifier 1. Enable logic level is High.
75
LIM1_VCC
Limiter amplifier 1 supply pin. Use high quality decoupling capacitors right at the pin.
76
LIM1_Out-
Negative output of limiter amplifier 1. Requires AC coupling.
77
LIM1_Out+
Positive output of limiter amplifier 1. Requires AC coupling.
78
GND
Ground. Connect to a solid ground plane.
79
RSSI_RL1
Load resistor to ground. Nominal value is 6kΩ. This load is used to terminate the LIM RSSI current output and
maintain temperature and process variation to a minimum.
80
LIM1_RSSI Current output of RSSI for the limiter amplifier 1. Connect in parallel with the RSSI output of the amplifier limiter 2
for cascaded response.
NOTES:
7. The HFA3724 generates a lower sideband signal when the “I” input leads the “Q” input by 90 degrees.
8. For a reference LO frequency higher than a CW IF signal input, the “I” channel leads the “Q” channel by 90 degrees.
9. The in-phase reference LO transitions occur at the rising edges of the 2XLO clock signal. Quadrature LO transitions occur at the falling edges.
180 degrees phase ambiguity is expected for carrier locked systems without differential encoding.
LIM1_PE
LIM2_PE
LPF_RX_PE
MOD_RX_PE
MOD_TX_PE
LPF_TX_PE
TABLE 1. POWER MANAGEMENT
TRANSMIT
RECEIVE
0
1
0
1
0
1
0
1
1
0
1
0
POWER DOWN
0
0
0
0
0
0
8
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