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IS1002

Bluetooth Baseband Controller

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創傑科技股份有限公司

Integrated System Solution Corp.

IS1002

Bluetooth Baseband Controller

7. Functional Description

7.1 Overall Architecture

The ISSC IS1090 integrates an enhanced Bluetooth core, HCI controller, Audio controller

and an embedded Turbo 8051 processor with 160K mask ROM for program memory and

32K SRAM for data memory. An innovative interconnection structure called the Common-

Memory Architecture (CMA) is designed to provide a fast and flexible data movement

scheme between the embedded processor, Bluetooth core, and peripheral hardware.

7.2 Embedded Processor

The embedded processor is the Turbo 8051 CPU. The embedded processor will be

referred to as simply the processor or 8051 throughout the remainder of this document.

7.3 Common Memory Bus Architecture (CMA)

The functional diagram describing the CMA is shown in figure 1. A single-port synchronous

interface is provided to memory. From this single port, the bandwidth is divided among the

6 interface busses described below:

• Embedded processor bus

• Baseband TX bus

• Baseband RX bus

• HCI TX bus

• HCI RX bus

• Audio bus

In addition, attached to the embedded processor bus are a register bank, a dedicated

single-port memory (data segment 1), and flash memory (program segment). The

processor coordinates all link control procedures and data movement using a set of pointer

registers. For example, when an HCI packet (from the host via USB or UART) is received

into the HCI buffer, the processor is interrupted. The processor can then read a status

register to determine the HCI packet type and determine whether to set up the Baseband

pointer registers for this memory region for RF-retransmission, or to otherwise directly

perform packet processing with the CPU.

Preliminary Datasheet

page 6

Released date: July 2004

Revision 0.9

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