M38B59MD-XXXFS Ver la hoja de datos (PDF) - Renesas Electronics
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M38B59MD-XXXFS Datasheet PDF : 70 Pages
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MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
PWM control register
(PWMCON: address 002616)
P87/PWM output selection bit
0: I/O port
1: PWM output
Not used (return “0” when read)
Fig. 55 Structure of PWM Control Register
PWM register
(high-order)
PWM register
(low-order)
PWM latch
(14-bit)
Data 6A16 stored at address 001416
5916
6A16
Data 7B16 stored at address 001416
7B16
Data 2416 stored at address 001516
Bit 7 cleared after transfer
Data 3516 stored at address 001516
1316
A416
2416
3516
Transfer from register to latch
B516
Transfer from register to latch
165316
1A9316
1AA416
1AA416
1EE416
1EF516
T = 4096 µs
(64 ! 64 µs)
When bit 7 of PWML is “0,” transfer
from register to latch is disabled.
t = 64 µs
(Example 1)
PWM output
1
6A 6B 6A 6B 6A 6B 6A 6B 6A 6B 6B 6B 6A 6B 6A 6B 6A 6B 6A
Low-order 6-bits
output
5
H = 6A16
L = 2416
5
5
5
6B16............36 times
(107)
525
5
6A16............28 times
(106)
5
5
5
106 ! 64 + 36
6B 6A 6B 6A 6B 6A 6B 6A
5
5
5
5
(Example 2)
PWM output
6A 6A 6A 6A 6B 6A 6B 6A 6B 6A 6A 6A 6B 6A 6B 6A 6B 6A 6A
6A 6B 6A 6B 6A 6B 6A 6A
Low-order 6 bits
output
H = 6A16
L = 1816
4
3
4
4
3
6B16............24 times
6A16............40 times
4
106 ! 64 + 24
4
3
4
Minimum bit width τ = 0.25 µs
t = 64 µs
(256 ! 0.25 µs)
PWM output
2
8-bit counter
6B 6A 69 68 67
ADD
02 01 00 FF FE FD FC
……… 02 01
……… 97 96 95
………
6A 69 68 67
ADD
02 01 00 FF FE FD FC
………
………
02 01
97 96 95
.............
The ADD portions with
additional τ are determined
either “H” or “L” by low-order
6-bit data.
“H” period length specified by PWMH
256 τ(64 µs), fixed
Fig. 56 14-bit PWM Timing
50
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