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MAX1206ETL

40Msps, 12-Bit ADC

Maxim Integrated 

40Msps, 12-Bit ADC

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1µF, CL ≈ 5pF at digital outputs, VIN =

-0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1µF to GND, 1µF

in parallel with 10µF between REFP and REFN, CCOM = 0.1µF in parallel with 2.2µF to GND, TA = -40°C to +85°C, unless otherwise

noted. Typical values are at TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

Digital Output Supply Current

IOVDD

TIMING CHARACTERISTICS (Figure 5)

Clock Pulse-Width High

tCH

Clock Pulse-Width Low

tCL

Data Valid Delay

tDAV

Data Setup Time Before Rising

Edge of DAV

tSETUP

Normal operating mode,

fIN = 20MHz at -0.5dBFS,

OVDD = 2.0V, CL ≈ 5pF

Power-down mode; clock idle,

PD = OVDD

CL = 5pF (Note 5)

CL = 5pF (Notes 3, 5)

6.1

mA

6

µA

12.5

ns

12.5

ns

6.4

ns

13.9

ns

Data Hold Time After Rising Edge

of DAV

Wake-Up Time from Power-Down

tHOLD

tWAKE

CL = 5pF (Notes 3, 5)

VREFIN = 2.048V

10.7

ns

10

ms

Note 1: Specifications ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.

Note 2: Specifications guaranteed by design and characterization. Devices tested for performance during production test.

Note 3: Guaranteed by design and characterization.

Note 4: During power-down, D11–D0, DOR, and DAV are high impedance.

Note 5: Digital outputs settle to VIH or VIL.

6 _______________________________________________________________________________________

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