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MAX17075
(Rev.:2008)

Boost Regulator with Integrated Charge Pumps, Switch Control, and High-Current Op Amp

Maxim Integrated 

Boost Regulator with Integrated Charge Pumps,

Switch Control, and High-Current Op Amp

PIN

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18, 19

20

21

22

23

24

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NAME

POS

NEG

OUT

BGND

SUP

DRVP

DRVN

CTL

RST

FBP

FBN

REF

VCC

AGND

RSTIN

COMP

FB

PGND

LX

DRN

COM

SRC

DEL

EP

Pin Description

FUNCTION

Operational Amplifier Noninverting Input

Operational Amplifier Inverting Input

Operational Amplifier Output

Analog Ground for Operational Amplifier and Charge Pump. Connect to AGND underneath the IC.

Operational Amplifier and Charge-Pump Supply Input. Connect this pin to the output of the boost

regulator (AVDD) and bypass to BGND with a minimum1μF capacitor.

Positive Charge-Pump Driver Output

Negative Charge-Pump Driver Output

High-Voltage Switch Control Input. When CTL is high, the switch between GON and SRC is on and the

switch between GON and DRN is off. When CTL is low, the switch between GON and DRN is on and the

switch between GON and SRC is off. CTL is inhibited by VCC UVLO and when DEL is less than 1.25V.

Reset Output. RST is an open-drain output.

Positive Charge-Pump Regulator Feedback Input. Connect FBP to the center of a resistive voltage-

divider between the positive charge-pump regulator output and AGND to set the positive charge-pump

regulator output voltage. Place the resistive voltage-divider within 5mm of FBP.

Negative Charge-Pump Regulator Feedback Input. Connect FBN to the center of a resistive voltage-

divider between the negative output and REF to set the negative charge-pump regulator output voltage.

Place the resistive voltage-divider within 5mm of FBN.

Reference Output. Connect a 0.22μF capacitor from REF to AGND. All power outputs are disabled until

REF exceeds its UVLO threshold.

Supplies the Internal Reference and Other Internal Circuitry. Connect VCC to the input supply voltage

and bypass VCC to AGND with a minimum 1μF ceramic capacitor.

Analog Ground for Step-Up Regulator and Linear Regulators. Connect to power ground (PGND)

underneath the IC.

Reset Input. Connect to the center of a resistor-divider from VIN.

Compensation Pin for Error Amplifier. Connect a series RC from COMP to AGND.

Step-Up Regulator Feedback Input. Connect FB to the center of a resistive voltage-divider between the

step-up regulator output and AGND to set the regulator’s output voltage. Place the resistive voltage-

divider within 5mm of FB.

Power Ground

Step-Up Regulator Switching Node. Connect inductor and catch diode here and minimize trace area for

lowest EMI power ground.

Switch Input. Drain of the internal high-voltage back-to-back p-channel FET connects to COM.

Internal High-Voltage MOSFET Switch Common Terminal

Switch Input. Source of the internal high-voltage pFET. Bypass SRC to PGND with a minimum 0.1μF

capacitor close to the pin.

High-Voltage Switch Delay Input. Connect a capacitor from DEL to AGND to set delay.

Exposed Pad. Connect to AGND.

10 ______________________________________________________________________________________

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