![](/html/MaximIC/159881/page11.png)
10Gbps Clock and Data Recovery
with Limiting Amplifier
VCC
50Ω
50Ω
SDO+
SDO-
GND
Figure 7. CML Output Model
(SDI+) - (SDI-)
(SDO+) - (SDO-)
POL = VCC
(SDO+) - (SDO-)
POL = GND
Figure 8. Polarity (POL) Function
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