MAX3882A Ver la hoja de datos (PDF) - Maxim Integrated

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MAX3882A

2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier

Maxim Integrated 

2.488Gbps 1:4 Demultiplexer with Clock and

Data Recovery and Limiting Amplifier

+3.3V

0.068μF

+3.3V

155MHz

CLOCK

SIS

FIL VCC LREF LOL

PD3+

SLBI+

PD3-

SLBI-

PD2+

MAX3882A

PD2-

0.1μF

SDI+

TIA OUTPUT

AGC

SDI-

PD1+

0.1μF

VCTRL

PD1-

MAX3861

R1

VREF

R2

PD0+

R1 + R2 ≥ 50kΩ

PD0-

PCLK+

FREFSET CAZ+ CAZ-

PCLK-

+3.3V

0.1μF

*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.

THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω.

Figure 8. Connecting the MAX3882A with Threshold Adjust and Clock Holdover Enabled

VCC

100Ω*

100Ω*

OVERHEAD

100Ω* TERMINATION

100Ω*

100Ω*

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