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PI90LV211L

16 differential clock distribution chip

Pericom Semiconductor 

PI90LV211/PI90LVT211

1:6 Differential Clock

Distribution Chip 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122

Switching Characteristics over Recommended Operating Conditions (unless otherwise noted)(8,9).

Characteristic

Symbol Min.

Typ.

Max.

Units

Condition

Propagation Delay to Output

CLK to CLKOUT ±

SCLK to CLKOUT ±

SEL to CLKOUT ±

Disable Time

CLK or SCLK to CLKOUT ±

Part-to-Part Skew

CLK (Diff) to Q

CLK (SE), SCLK to Q

With Device Skew

tPLH

1.5

2.7

3.4

tPHL

1.5

2.7

3.24

1.5

2.7

3.6

ns

tPHZ

2.2

2.8

tPLZ

2.1

2.8

tPZH

3.6

4.8

2

tPZL

2.8

4.8

tskew

TBD

TBD

1

TBD

Cycle-to-Cycle Jitter

Period Jitter

Setup Time

ENx to CLK

CEN to CLK

tjit(cc)

–48

+48

tjit(per)

–24

+24

ts

200

–100

200

0

Figure 6

ps

Figure 7

2

Hold Time

CLK to ENx, CEN

th

600

760

2

Minimum Input Swing (CLK)

Com. Mode Range (CLK)

VPP

0.20

0.800

3

V

VCMR

0.125

1.5

VCC - 0.2

4

Rise/Fall Times

20 – 80%

tr, tf

150

400

1200

Duty Cycle Distortion Pulse Skew ( tPLH - tPHL)

SCLK to CLKOUT±

CLK to CLKOUT±

tSK1R

tSK1R

140

180

ps

5

25

60

Channel-to-Channel Skew, same edge

tSK2R

30

100

6

Maximum Operating Frequency

250

MHz

7

Notes:

1. Within-Device skew is defined for identical transitions on similar paths through a device.

2. Setup, Hold, and Disable times are all relative to a falling edge on CLK or SCLK.

3. Minimum input swing for which AC parameters are guaranteed. Full DC LVDS output swings will be generated with only 50mV input

swings.

4. The range in which the high level of the input swing must fall while meeting the VPP spec.

5. tSKIR is the difference in receiver propagation delay (tPLH-tPHL) of one device, and is the duty cycle distortion of the output at any given

temperature and VCC. The propagation delay specification is a device-to-device worst case over process, voltage, and temperature.

6. tSK2R is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction. This

parameter is guaranteed by design and characterization.

7. Generator input conditions: trtf < 1ns, 50% duty cycle, differential (1.10V to 1.35V peak-peak).

Output Criteria: 60%/40% duty cycle, VOL (max) 0-4V, VOH (min) 2.7V, Load - 7pF (stray plus probes).

8. CL includes probe and fixture capacitance.

9. Generator waveform for all tests unless otherwise specified: f = 25 MHz, ZO = 50 ohms, tr = 1ns, tf = 1ns (35%-65%). To ensure fastest propagation

delay and minimum skew, clock input edge rates should not be slower than 1ns/V; control signals not slower than 3ns/V.

3

PS8535C 10/04/04

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