M48Z12(2003) Ver la hoja de datos (PDF) - STMicroelectronics
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| M48Z12 Datasheet PDF : 0 Pages | |||
M48Z02, M48Z12
Data Retention Mode
With valid VCC applied, the M48Z02/12 operates
as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self when VCC falls within the VPFD (max), VPFD
(min) window. All outputs become high imped-
ance, and all inputs are treated as “don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's con-
tent. At voltages below VPFD (min), the user can be
assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48Z02/12 may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
The power switching circuit connects external VCC
to the RAM and disconnects the battery when VCC
rises above VSO. As VCC rises, the battery voltage
is checked. If the voltage is too low, an internal
Battery Not OK (BOK) flag will be set. The BOK
flag can be checked after power up. If the BOK flag
is set, the first WRITE attempted will be blocked.
The flag is automatically cleared after the first
WRITE, and normal RAM operation resumes. Fig-
ure 9 illustrates how a BOK check routine could be
structured.
For more information on a Battery Storage Life re-
fer to the Application Note AN1012.
Figure 9. Checking the BOK Flag Status
POWER-UP
READ DATA
AT ANY ADDRESS
WRITE DATA
COMPLEMENT BACK
TO SAME ADDRESS
READ DATA
AT SAME
ADDRESS AGAIN
IS DATA
COMPLEMENT
OF FIRST
READ?
(BATTERY OK) YES
WRITE ORIGINAL
DATA BACK TO
SAME ADDRESS
NO (BATTERY LOW)
NOTIFY SYSTEM
OF LOW BATTERY
(DATA MAY BE
CORRUPTED)
CONTINUE
AI00607
Figure 10. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tPD
tFB
INPUTS
RECOGNIZED
tDR
tRB
DON'T CARE
tR
NOTE
tREC
RECOGNIZED
OUTPUTS
VALID
HIGH-Z
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI00606
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E high as VCC rises past VPFD (min). Some systems
may perform inadvertent WRITE cycles after VCC rises above VPFD (min) but before normal system operations begin. Even though a
power on reset is being applied to the processor, a reset condition may not occur until after the system is running.
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