MAX7369EUP Ver la hoja de datos (PDF) - Maxim Integrated
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MAX7369EUP Datasheet PDF : 19 Pages
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4-Channel I2C Switches/Multiplexer
TIMING CHARACTERISTICS (Figure 1) (continued)
(VDD = 2.3V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
Fall Time of Both SDA and SCL
Signals
SYMBOL
tf
CONDITIONS
fSCL = 100kHz
fSCL = 400kHz (Note 5)
Capacitive Load for Each Bus Line
Pulse Width of Spikes Suppressed
Data Valid Time from High to Low
Data Valid Time from Low to High
Data Valid Acknowledge
INT (Figure 2)
INT_ to INT Active Valid Time
INT_ to INT Inactive Delay Time
Low-Level, Pulse-Width Rejection
or INT_ Inputs
Cb
tSP
tVD;DATL
tVD;DATH
tVD;ACK
(Note 6)
(Note 7)
(Note 7)
tIV
tIR
tW(REJ)L
MIN TYP MAX UNITS
300
20 +
0.1Cb
ns
300
400
pF
50
ns
1
µs
0.6
µs
1
µs
4
µs
2
µs
1
µs
High-Level, Pulse-Width Rejection
or INT_ Inputs
tW(REJ)H
0.5
µs
RESET (Figure 3)
Pulse-Width Low Reset
Reset Time (SDA Clear)
tWL(RST)
tRST
4
ns
500
ns
Recovery to Start
tREC;STA
0
ns
Note 1: All parameters are production tested at TA = +25°C and guaranteed by design over the specified temperature range.
Note 2: Minimum value is not production tested. Guaranteed by design.
Note 3: Pass gate propagation delay is calculated from 20Ω (typ) RON and the 15pF load capacitance. Not production tested.
Note 4: A master device must provide a hold time of at least 300ns for the SDA signal (referred to the VIL of the SCL) in order to
bridge the undefined region of SCL’s falling edge.
Note 5: Cb = total capacitance of one bus line in pF.
Note 6: Guaranteed by design.
Note 7: Measurements taken with a 1kΩ pullup resistor and 50pF load.
SDA
tf
SCL
S
tLOW
tHD;STA
tSU;DAT
tr
tf
tHD;STA
tHD;DAT
tHIGH
tSU;STA
Sr
tSP
tr
tBUF
tSU;STO
P
S
Figure 1. 2-Wire Serial-Interface Timing Diagram
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