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MC100E211

5V ECL 1:6 Differential Clock Distribution Chip

ON Semiconductor 

MC10E211, MC100E211

5VĄECL 1:6 Differential

Clock Distribution Chip

The MC10E/100E211 is a low skew 1:6 fanout device designed

explicitly for low skew clock distribution applications.

The E211 features a multiplexed clock input to allow for the

distribution of a lower speed scan or test clock along with the high speed

system clock. When LOW (or left open in which case it will be pulled

LOW by the input pulldown resistor) the SEL pin will select the

differential clock input.

Both a common enable and individual output enables are provided.

When asserted the positive output will go LOW on the next negative

transition of the CLK (or SCLK) input. The enabling function is

synchronous so that the outputs will only be enabled/disabled when the

outputs are already in the LOW state. In this way the problem of runt

pulse generation during the disable operation is avoided. Note that the

internal flip flop is clocked on the falling edge of the input clock edge,

therefore all associated specifications are referenced to the negative

edge of the CLK input.

The output transitions of the E211 are faster than the standard

ECLinPS edge rates. This feature provides a means of distributing

higher frequency signals than capable with the E111 device. Because of

these edge rates and the tight skew limits guaranteed in the

specification, there are certain termination guidelines which must be

followed. For more details on the recommended termination schemes

please refer to the applications information section of this data sheet.

The VBB pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

differential input is connected to VBB as a switching reference voltage.

VBB may also rebias AC coupled inputs. When used, decouple VBB

and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to

0.5 mA. When not used, VBB should be left open.

The 100 Series contains temperature compensation.

• Guaranteed Low Skew Specification

• Synchronous Enabling/Disabling

• Multiplexed Clock Inputs

• VBB Output for Single-Ended Use

• Common and Individual Enable/Disable Control

• High Bandwidth Output Transistors

• PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V

• NECL Mode Operating Range: VCC= 0 V with VEE= –4.2 V to –5.7 V

• Internal Input Pulldown Resistors

• ESD Protection: > 2 KV HBM, > 100 V MM

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

• Moisture Sensitivity Level 1

For Additional Information, see Application Note AND8003/D

• Flammability Rating: UL–94 code V–0 @ 1/8”,

Oxygen Index 28 to 34

• Transistor Count = 457 devices

http://onsemi.com

MARKING

DIAGRAMS

MC10E211FN

AWLYYWW

PLCC–28

FN SUFFIX

28 1

CASE 776

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

MC100E211FN

AWLYYWW

28 1

ORDERING INFORMATION

Device

Package

Shipping

MC10E211FN

PLCC–28 37 Units/Rail

MC10E211FNR2 PLCC–28 500 Units/Reel

MC100E211FN

PLCC–28 37 Units/Rail

MC100E211FNR2 PLCC–28 500 Units/Reel

© Semiconductor Components Industries, LLC, 2001

1

February, 2001 – Rev. 5

Publication Order Number:

MC10E211/D

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