¡ Semiconductor
RS
R * CK
4020
(A)
CD
R * CK
4020
(B)
R * CK
4020
(C)
MSM6926/6946
RS1
RS2
VD
TS1
VD
TS2
Q CK
QD
CD1
CD2
873.9 Hz
CLK
(A) RS/CS delay, (B) CD/ON delay, (C) CD/OFF delay
Note: Supply voltage equals VD for all gates.
*: The desired delay can be realized by selecting the appropriate bits from 4020's outputs.
The number of the bits is not always 3. Each delay can be set differently from built-in delays.
Figure 11 External Delays Connection
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