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MSM6926

300 bps Single Chip FSK MODEM

Oki Electric Industry 

¡ Semiconductor

MSM6926/6946

Control

Name

LT

CC

RS2

CD1

CD2

RD1

RD2

CDR1

CDR2

M

FT

TS1

TS2

Pin No.

I/O

RS GS-K

Description

Digital loop back test. During digital "High", any data sent on the XD pin will appear

on the RD pin, and any data sent on the RS1 pin will immediately appear on the

4 44 I CS pin. Any data demodulated from the received carrier on the AIN pin will be the

modulated data to implement the transmitted carrier. In this case, sending the

transmitted carrier to the phone line depends on the CC, but never on RS1.

5

2

I

During digital loop back test, the data on this pin becomes a control signal for sending

the transmitted carrier to the phone line in place of RS1.

When an external circuit gives the RS/CS delay time which is not within the device

8 8 I as required, this pin should be connected to the external circuit output.

See Fig. 11.

The fast carrier detection output. This pin is internally connected to the input of

11

12

O

the built-in carrier detect delay circuit. When an external delay circuit provides

the delay time which is not within the device as required, the CD1 should be

connected to the external circuit input. See Fig. 11.

When an external circuit gives the carrier detect delay time which is not within

the device as required, this pin becomes the input pin for the external circuit

12 13 I/O output signal. In other cases (when using the delay time within the device, the

data on the TS1 or TS2 is not digital "High"), this pin becomes the Carrier detect

signal output.

The RD1 data is demodulated data from the received carrier and the RD2 is the

13 14 O input of the following logic circuits referred to in Fig. 12. Usually, the RD1 data

is input directly to RD2. In some cases, as input data to RD2, the data that is

14 16

I controlled by NCU (Network control unit) etc. may be required in stead of the

RD1 data.

These two pins are the output (CRD1) and inverting input (CDR2) of the buffer

16 20 O operational amplifier of which the noninverting input is connected to the built-in

voltage reference, stabilized to variations in the supply voltage and temperature.

See Fig. 13. An adequate carrier-detect level can be set by selecting the ratio of

17 21

R8 to R9. Therefore, the loss in the received carrier level by phone-line

I transformer can be compensated by adjusting the ratio of R8 to R9. R8 + R9

should be greater than 50 kW.

22 31

I

Answer/Originate mode select. During digital "High", the originate mode is

selected. A low input selects the answer mode.

23 32

I

This pin may be used for device tests only. During digital "High", the AO pin will

be connected to receiving filter output instead of transmitting filter output.

27 36

28 38

RS/CS delay and carrier detect delay options referred to chapter about timing

I characteristics are selected by TS1 and TS2 inputs. Be careful that each delay

can not be individually selected. If another delay time than the ones within the

device are required as an option, input a digital "High" to the TS1 and TS2 pin

and implement the external delay circuits to obtain the desired delay

I characteristics. In this case, the CD2 pin becomes not only the input for the

external circuit output signal, but also the Carrier detect output. See Fig. 11.

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