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PI74ALVCH16244A Ver la hoja de datos (PDF) - Pericom Semiconductor

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PI74ALVCH16244A
Pericom-Semiconductor
Pericom Semiconductor Pericom-Semiconductor
PI74ALVCH16244A Datasheet PDF : 4 Pages
1 2 3 4
PI74ALVCH16244 111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222
16-Bit Buffer Driver
with 3-State Outputs
Product Features
PI74ALVCH16244 is designed for low-voltage operation
VCC = 2.3V to 3.6V
Hysteresis on all inputs
Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
Industrial operation at –40°C to +85°C
Packages available:
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor’s PI74ALVCH series of logic circuits
are produced using the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The PI74ALVCH16244 is an non-inverting 16-bit buffer/driver
designed for low-voltage 2.3V to 3.6V VCC operation.
The buffer/driver is designed specifically to improve both the
performance and density of 3-State memory address drivers, clock
drivers, and bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two 8-bit buffers, or
one 16-bit buffer. It provides inverting outputs and symmetrical
active-low output-enable (OE) inputs.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor in which
the minimum value is determined by the current-sinking capability
of the driver.
The PI74ALVCH16244 has “Bus Hold” which retains the data
input’s last state whenever the data input goes to high-impedance
preventing “floating” inputs and eliminating the need for pullup/
down resistors.
Logic Block Diagram
1OE 1
1A1 47
46
1A2
1A3 44
43
1A4
2 1Y1
3
1Y2
5 1Y3
6
1Y4
3OE 25
3A1 36
35
3A2
3A3 33
32
3A4
13 3Y1
14
3Y2
16 3Y3
17
3Y4
2OE 48
2A1 41
40
2A2
38
2A3
37
2A4
8 2Y1
9 2Y2
11 2Y3
12 2Y4
4OE 24
4A1 30
29
4A2
27
4A3
26
4A4
19 4Y1
20
4Y2
22
4Y3
23
4Y4
1
PS8087B 07/28/00

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