MX98745 Ver la hoja de datos (PDF) - Macronix International
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MX98745 Datasheet PDF : 36 Pages
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MX98745
B. Expansion Port, 12 pins
PAD # Name
65
JAMO
66
JAMI
68
EDENL
63-59 EDAT[4:0]
64
EPCLK
70
ANYACT
67
EDCRS
71
EDACT
I/O
O,
CMOS
I,
TTL
I,
Sche
I/O,
TTL
I/O,
TTL
O,
CMOS
I,
Sche
O,
CMOS
Description
Forced Jam Out. Active High. The OR’d forced jam signals controlled by
Carrier Integrity Monitor of each port. If collision occurs inside the XRC II
(exclude JAMI), this pin is also asserted.
Forced Jam Input. Active High. Asserted by external arbitor, and XRCII will
generate JAM patterns to all its ports whenever this signal is validate more
than 40 ns. This signal is filtered by LSCLK for 40ns internally.
Enable Expansion Data. Active Low. Asserted by an external arbitor. XRC II
will not drive data onto EDAT until this pin is asserted. Assertion time less
than 40ns will not be recognized by XRC II.
Expansion Data. Bidirectional 5 bit-wide data. By default, EDAT is an input.
An external arbitor coordinates multiple devices on EDAT.
Expansion port Data Clock. This clock will be outputed by XRCII along with
the EDAT[4:0]. Another module of XRCII should use this signal as expansion
port data input clock.
Any Activity. Active High. When XRCII tries to release data onto EDAT, this
pin will be asserted by XRC II.
Expansion Data Carrier Sense. When this pin is asserted, XRC II will
recognize that there is activity on expansion port data bus EDAT and perform
corresponding activity within XRCII itself.
Expansion Data Activity. When XRCII detects that EDENL is asserted by
external arbitor, it will assert EDACT high. System application can use this
signal to control the data bus flow of EDAT.
Table 5-1 Pin Description for XRC II (Continued)
P/N:PM0427
REV. 1.4, JUL. 8, 1998
5
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