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PCD5002

Advanced POCSAG and APOC-1 Paging Decoder

Philips Electronics 

Philips Semiconductors

Advanced POCSAG and APOC-1 Paging

Decoder

Product specification

PCD5002

Codewords received at the expected sync word positions

(POCSAG batch size) are matched against standard

POCSAG sync word, all enabled UPSWs and preamble.

Data output to an external controller is initiated by an

interrupt at the next sync word position, after reception of

16 codewords.

The call header preceding the data has a different

structure from normal POCSAG or APOC-1 data. The data

header format is shown in Table 12.

Continuous data decoding continues until one of the

following conditions occur:

• The decoder is switched to the OFF state

• A Forced Call Termination (FCT) command is received

via the I2C-bus

• Preamble is detected at the sync word position

• Standard POCSAG sync word or an enabled non-CDD

sync word is detected.

Only a forced call termination command will be indicated in

the SRAM data by a call terminator. In the other events

continuous data decoding will stop without notification.

Upon forced termination the ‘fade recovery’ mode is

entered. Detection of preamble causes the device to

switch to the ‘preamble receive’ mode. Detection of a

standard sync word or any enabled non-continuous UPSW

will cause the device to switch to the ‘data receive’ mode.

Continuous data decoding will continue in the next batch if

any enabled CDD sync word is detected or no enabled

sync word is detected.

8.20 Receiver and oscillator control

A paging receiver and an RF oscillator circuit can be

controlled independently via enable outputs RXE and ROE

respectively. Their operating periods are optimized

according to the synchronization mode of the decoder.

Each enable signal has its own programmable

establishment time (see Table 14).

8.21 External receiver control and monitoring

An external controller may enable the receiver control

outputs continuously via an I2C-bus command, overruling

the normal enable pattern. Data reception continues

normally. This mode can be exited by means of a reset or

an I2C-bus command.

External monitoring of the receiver control output RXE is

possible via bit D6 in the status register, when enabled via

the control register (D2 = 1). Each change of state of

output RXE will generate an external interrupt at

output INT.

Table 12 Continuous data header format

BYTE NUMBER

1

2

3

BIT 7

(MSB)

0

0

X

BIT 6

X

C3

X

BIT 5

X

C2

F0

BIT 4

X

C1

F1

BIT 3

C3

C3

E3

BIT 2

C2

C2

E2

BIT 1

C1

C1

E1

BIT 0

(LSB)

0

0

0

Table 13 Data header bit identification

BITS (MSB to LSB)

C3 to C1

F0 and F1

E3 to E1

IDENTIFICATION

identifier number of continuous data decoding sync word

function bits of received address codeword (bits 20 and 21)

detected error type (see Table 11); E3 = 0 in a concatenated call header

1997 Jun 24

16

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