PI5A3159
SOTINYTM 1Ω Low-Voltage
SPDT Analog Switch
Test Circuits/Timing Diagrams
VCOM
Logic
Input
V+
V+
NC
NO
RL
VNO
CL RL
50Ω 35pF 50Ω
GND
VOUT
CL
35pF
CL INCLUDES FIXTURE AND STRAY CAPACITANCE
( ) VOUT = VNO
RL
RL + RON
Logic VINH
Input
VINL
50%
tr <20ns
tf <20ns
tOFF
Switch
Output 0V
VOUT 90%
tON
90%
LOGIC INPUT WAVEFORMS INVERTED FOR
SWITCHES THAT HAVE OPPOSITE LOGIC
* 1.5V FOR 3.3V SUPPLY
Figure 1. Switching Time
V+
VGEN
Logic
Input
.1µF
NO or
NC
V+
COM
IN
GND
VOUT
CL
1nF
VOUT
IN
OFF
OFF
IN
Figure 2. Charge Injection
ON
ON
Q = (∆VOUT)(CL)
∆VOUT
OFF
OFF
VIN
Logic
Input
V+
V+
NC
COM
NO
IN
GND
VOUT
RL
CL
50Ω 35pF
Logic VINH
Input VINL
Switch
Output
(VOUT)
50%
0.9xVOUT
tBBM
CL INCLUDES FIXTURE AND STRAY CAPACITANCE
Figure 3. Break-Before-Make Interval
0.9xVOUT
PS8634C
09/13/04
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