PI6C2510-133LE Ver la hoja de datos (PDF) - Pericom Semiconductor Corporation
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PI6C2510-133LE
Pericom Semiconductor Corporation
PI6C2510-133LE Datasheet PDF : 5 Pages
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PI6C2510-133
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Low-Noise, Phase-Locked Loop
Clock Driver with 10 Clock Outputs
Features
• Operating Frequency up to 150 MHz
• Low-Noise Phase-Locked Loop Clock Distribution that
meets 133 MHz Registered DIMM Synchronous DRAM
modules for server/workstation/PC applications
• Allows Clock Input to have Spread Spectrum modulation
for EMI reduction
• Zero Input-to-Output delay: Distribute one Clock Input
to one Bank of Ten outputs, with an output enable.
• Low jitter: Cycle-to-Cycle jitter ±75ps max.
• On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
• Operates at 3.3V VCC
• Packaging(Pb-free & Green available):
- 24-pin TSSOP (L)
Description
The PI6C2510-133 is a “quiet,” low-skew, low-jitter, phase-locked
loop (PLL) clock driver, distributing high-frequency clock signals
for SDRAM and server applications. By connecting the feedback
FB_OUT output to the feedback FB_IN input, the propagation
delay from the CLK_IN input to any clock output will be nearly zero.
This zero-delay feature allows the CLK_IN input clock to be
distributed, providing one clock input to one bank of ten outputs,
with an output enable.
This clock driver is designed to meet the PC133 SDRAM Registered
DIMM specification. For test purposes, the PLL can be bypassed
by strapping AVCC to ground.
Block Diagram
G
CLK_IN
PLL
FB_IN
AVcc
Pin Configuration
10
Y[0:9]
FB_OUT
AGND
VCC
Y0
Y1
Y2
GND
GND
Y3
Y4
VCC
G
FB_OUT
1
24
2
23
3
22
4
21
5 24-Pin 20
6
L 19
7
18
8
17
9
16
10
15
11
14
12
13
CLK_IN
AVCC
VCC
Y9
Y8
GND
GND
Y7
Y6
Y5
VCC
FB_IN
Functional Table
Inputs
Outputs
G
Y[0:9] FB_OUT
L
L
CLK_IN
H
CLK_IN CLK_IN
1
PS8383B 09/14/04
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