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MT93L16AQ

Low-Voltage Acoustic Echo Canceller

Mitel Networks 

MT93L16

Register Summary

Preliminary Information

Address:

00h R/W

Power Up

Reset 00h

RESET

AH-

AGC-

NB-

BYPASS

MUTE_S

MUTE_R

LIMIT

Main Control Register (MC)

7 LIMIT 6 MUTE_R 5 MUTE_S 4 BYPASS 3 NB- 2 AGC- 1 AH-

MSB

0 RESET

LSB

When high, the power initialization routine is executed presetting all registers to default values.

This bit automatically clears itself to’0’ when reset is complete.

When high, the Howling detector is disabled and when low the Howling detector is enabled.

When high, AGC is disabled and when low AGC is enabled.

When high, Narrowband signal detectors in Rin and Sin paths are disabled and when low the signal detectors are enabled

When high, the Send and Receive paths are transparently by-passed from input to output and when low the Send and

Receive paths are not bypassed

When high, the Sin path is muted to quite code (after the NLP) and when low the Sin path is not muted

When high, the Rin path is muted to quite code (after the NLP) and when low the Rin path is not muted

When high, the 2-bit shift mode is enabled in conjunction with bit 7 of LEC register and when low 2-bit shift mode is

disabled

Address:

21h R/W

Power Up

Reset 00h

ECBY

ADAPT-

HCLR

HPF-

INJ-

NLP-

ASC-

P-

Acoustic Echo Canceller Control Register (AEC)

7 P-

MSB

6 ASC- 5 NLP- 4 INJ-

3 HPF- 2 HCLR

1 ADAPT- 0 ECBY

LSB

When high, the Echo estimate from the filter is not subtracted from the input (Sin), when low the estimate is subtracted

When high, the Echo canceller adaptation is disabled and when low the adaptation is enabled

When high, Adaptive filter coefficients are cleared and when low the filter coefficients are not cleared

When high, Offset nulling filter is bypassed in the Sin/Sout path and when low the Offset nulling filter in not bypassed

When high, the Noise filtering process is disabled in the NLP and when low the Noise filtering process is enabled

When high, the Non Linear Processor is disabled in the Sin/Sout path and when low the NLP is enabled

When high, the Internal Adaptation speed control is disabled and when low the Adaptation speed is enabled

When high, the Exponential weighting function for the adaptive filter is disabled and when low the weighting function is

enabled

Address:

01h R/W

Power Up

Reset 00h

ECBY

ADAPT-

HCLR

HPF-

INJ-

NLP-

ASC-

SHFT

Line Echo Canceller Control Register (LEC)

7 SHFT 6 ASC- 5 NLP-

MSB

4 INJ-

3 HPF- 2 HCLR

1 ADAPT- 0 ECBY

LSB

When high, the Echo estimate from the filter is not substracted from the input (Rin), when low the estimate is substracted

When high, the Echo canceller adaptation is disabled and when low the adaptation is enabled

When high, Adaptive filter coefficients are cleared and when low the filter coefficients are not cleared

When high, Offset nulling filter is bypassed in the Rin/Rout path and when low the Offset nulling filter in not bypassed

When high, the Noise filtering process is disabled in the NLP and when low the Noise filtering process is enabled

When high, the Non Linear Processor is disabled in the Rin/Rout path and when low the NLP is enabled

When high, the Internal Adaptation speed control is disabled and when low the Adaptation speed is enabled

when high the 16-bit linear mode, inputs Sin, Rin, are shift right by 2 and outputs Sout, Rout are shift left by 2. This bit is

ignored when 16-bit linear mode is not selected in both ports. This bit is also ignored if bit 7 of MC register is set to zero

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