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RTL8201CP-VD

SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER (With Auto Crossover)

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RTL8201CP

Datasheet

6.2. Register 1 Basic Mode Status Register

Address

1:15

1:14

1:13

1:12

1:11

1:10~7

1:6

1:5

1:4

1:3

1:2

1:1

1:0

Table 10. Register 1 Basic Mode Status Register

Name

Description

100Base-T4 1: Enable 100Base-T4 support

0: Suppress 100Base-T4 support

100Base_TX_ FD 1: Enable 100Base-TX full duplex support

0: Suppress 100Base-TX full duplex support

100BASE_TX_HD 1: Enable 100Base-TX half duplex support

0: Suppress 100Base-TX half duplex support

10Base_T_FD 1: Enable 10Base-T full duplex support

0: Suppress 10Base-T full duplex support

10_Base_T_HD 1: Enable 10Base-T half duplex support

0: Suppress 10Base-T half duplex support

Reserved

MF Preamble The RTL8201CP will accept management frames with preamble

Suppression suppressed.

A minimum of 32 preamble bits are required for the first SMI

read/write transaction after reset. One idle bit is required

between any two management transactions as per IEEE 802.3u

specifications.

Auto Negotiation 1: Auto-negotiation process completed

Complete

0: Auto-negotiation process not completed

Remote Fault 1: Remote fault condition detected (cleared on read)

0: No remote fault condition detected

When in 100Base-FX mode, this bit means an in-band signal

Far-End-Fault has been detected. See 7.12 Far End Fault

Indication, page 22.

Auto Negotiation 1: Link has not experienced fail state

0: Link experienced fail state

Link Status 1: Valid link established

0: No valid link established

Jabber Detect 1: Jabber condition detected

0: No jabber condition detected

Extended Capability 1: Extended register capability

0: Basic register capability only

Mode

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Default

0

1

1

1

1

1

0

0

1

0

0

1

6.3. Register 2 PHY Identifier Register 1

Address

2:15~0

Name

PHYID1

Table 11. Register 2 PHY Identifier Register 1

Description

PHY identifier ID for software recognition of the RTL8201CP.

Mode Default

RO

0000

6.4. Register 3 PHY Identifier Register 2

Address

3:15~0

Name

PHYID2

Table 12. Register 3 PHY Identifier Register 2

Description

PHY identifier ID for software recognition of the RTL8201CP.

Mode Default

RO

8201

Single-Chip/Port 10/100 Fast Ethernet PHYceiver

9

Track ID: JATR-1076-21 Rev. 1.21

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