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SC18IM700 Datasheet PDF : 21 Pages
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Philips Semiconductors
SC18IM700
Master I2C-bus controller with UART interface
8. I2C-bus serial interface
The I2C-bus uses two wires (SDA and SCL) to transfer information between devices
connected to the bus, and it has the following features:
• Bidirectional data transfer between masters and slaves
• Multi-master bus (no central master)
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
A typical I2C-bus configuration is shown in Figure 12. The SC18IM700 device provides a
byte-oriented I2C-bus interface that supports data transfers up to 400 kHz.
I2C-bus
VDD
RPU
SC18IM700
RPU
I2C-BUS
DEVICE
Fig 12. I2C-bus configuration
9. Internal registers available
SDA
SCL
I2C-BUS
DEVICE
002aab801
9.1 Register summary
Table 4: Internal registers summary
Register Register
address
Bit 7
Bit 6
General register set
0x00
BRG0
bit 7
bit 6
0x01
BRG1
bit 7
bit 6
0x02
PortConf1 GPIO3.1 GPIO3.0
0x03
PortConf2 GPIO7.1 GPIO7.0
0x04
IOState
GPIO7 GPIO6
0x05
reserved bit 7
bit 6
0x06
I2CAdr
bit 7
bit 6
0x07
I2CClkL bit 7
bit 6
0x08
I2CClkH bit 7
bit 6
0x09
I2CTO
TO7
TO6
0x0A
I2CStat
1
1
Bit 5
bit 5
bit 5
GPIO2.1
GPIO6.1
GPIO5
bit 5
bit 5
bit 5
bit 5
TO5
1
Bit 4
bit 4
bit 4
GPIO2.0
GPIO6.0
GPIO4
bit 4
bit 4
bit 4
bit 4
TO4
1
Bit 3
Bit 2
Bit 1
Bit 0
R/W
bit 3
bit 2
bit 1
bit 0
R/W
bit 3
bit 2
bit 1
bit 0
R/W
GPIO1.1 GPIO1.0 GPIO0.1 GPIO0.0 R/W
GPIO5.1 GPIO5.0 GPIO4.1 GPIO4.0 R/W
GPIO3 GPIO2 GPIO1 GPIO0 R/W
bit 3
bit 2
bit 1
bit 0
-
bit 3
bit 2
bit 1
bit 0
R/W
bit 3
bit 2
bit 1
bit 0
R/W
bit 3
bit 2
bit 1
bit 0
R/W
TO3
TO2
TO1
TE
R/W
I2CStat[3] I2CStat[2] I2CStat[1] I2CStat[0] R
SC18IM700_1
Product data sheet
Rev. 01 — 28 February 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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