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SC18IM700

Master I2C-bus controller with UART interface

NXP Semiconductors. 

NXP Semiconductors

SC18IM700

Master I2C-bus controller with UART interface

15. Abbreviations

Table 16. Abbreviations

Acronym

Description

ASCII

American Standard Code for Information Interchange

FIFO

First In, First Out

GPIO

General Purpose Input/Output

I2C-bus

Inter Integrated Circuit bus

RX FIFO

Receive FIFO

TX FIFO

Transmit FIFO

UART

Universal Asynchronous Receiver/Transmitter

16. Revision history

Table 17. Revision history

Document ID

Release date

Data sheet status

Change notice Supersedes

SC18IM700_3

Modifications:

20171012

Product data sheet

201708035I

SC18IM700_2

• Added SC18IM700/S8

• Updated Section 4.1 “Ordering options”

• Section 2 “Features and benefits”: 9th bullet item: changed from “2.3 V and 3.6 V operation” to

“2.4 V and 3.6 V operation”

• Table 5 “Internal registers summary”:

– changed Default value for register IOState from “0x0F” to “-”

– added Table note [1]

SC18IM700_2

20070810

Product data sheet

-

SC18IM700_1

SC18IM700_1

20060228

Product data sheet

-

-

SC18IM700_3

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 12 October 2017

© NXP Semiconductors N.V. 2017. All rights reserved.

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