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CS5126

16-Bit, Stereo A/D Converter for Digital Audio

Cirrus Logic 

CDB5126

Sampling Clock Generation Logic

The CS5126 requires an external serial clock to

clock out the data. The CDB5126 board has the

logic necessary to generate the master clock,

HOLD, L/R, and SCLK to allow fast evaluation

of the ADC. In most systems, these timing sig-

nals will be available from the main timing

section, typically generated by a logic array of

some variety. HOLD may be brought in exter-

nally via a

BNC, optionally terminated by R29. SCLK and

L/R select may be brought in externally via test

points and removing jumpers.

Figure 5 shows the on-board clock generation

circuitry. U7 (74HC4040) produces binary di-

vided ratios of the 24.576 MHz master clock. Q4

generates a 1.5 MHz clock, which is used for

SCLK. Q8 generates a 96 kHz clock, used for

HOLD, and Q9 generates a 48 kHz clock, option-

ally used to toggle L/R select. This set of clocks

causes the CS5126 to continuously convert, gen-

erating a continuous stream of serial data bits. To

correctly identify the last bit of each word, U12

produces a pulse only when Q4, Q5, Q6, Q7, Q8,

and optionally Q9 are all high. This state is

latched by U10A to prevent any glitches, and the

resulting signal (attached to TP18) is used to

latch the U8-U9 shift registers.

Serial to Parallel Conversion

Figure 6 shows the serial to parallel conversion

circuit. Two 74HC595 shift register/latches con-

nected in series with SDATA assemble 16-bit,

parallel words, clocked by SCLK. As discussed

above, the outputs are latched inside the

74HC595 at the end of each 16-bit word. The

outputs are brought out to a 40-way header (P5).

Only low capacitance, twisted pair, ribbon cable

should be used.

+5VL

R16

p.4 R18

47 k

P4

47 k

12

U11

11

0 P10

1

2

13

+5VL

R19

47 k

P12

10

U11, pin 8

+5VL

14

8

C28 U6 OUT

Crystal

0.1 µF Oscillator

Module

7

C29

1 Q12

15 Q11

14 Q10

12 Q9

10 CLK

11 RST

8

0.1 µF

16

Q1 9

Q2 7

U7 Q3 6

Q4 5 R28

Q5 3 470

Q6 2

Q7 4

Q8 13

R16, p.5

47 k

C31

5

6

3 14

4 U12

12 7

2

R16, p.3

47 k

C32

0.1 µF

8

74HC30

2 14

U11

1

7

1

C30

0.1 µF

14

3

J

74HC00

24

0.1 µF

CLR Q 12

U10A

74HC73 Q 13

K

3

11

11

1

P9

P7

01

P1

(CLKIN)

P2

(HOLD)

P3

U8, U9

Shift CLK

Figure 5. Timing Generator

U8, U9

Latch CLK

DS32DB5

25

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