CS5126-KP Ver la hoja de datos (PDF) - Cirrus Logic

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CS5126-KP

16-Bit, Stereo A/D Converter for Digital Audio

Cirrus Logic 

CS5126

SWITCHING CHARACTERISTICS (TA = 25 °C; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%;

Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF)

Parameter

Symbol Min

Typ

Max Units

Master Clock Period

tclk

40

-

-

ns

HOLD to SSH2 Falling

(Note 10) tdfsh2

-

80

-

ns

HOLD to TRKL, TRKR

SSH1 Falling

tdfsh1 198tclk

-

214tclk+50 ns

HOLD to TRKL, TRKR

SSH1, SSH2 Rising

tdrsh

-

80

-

ns

RST Pulse Width

trst

150

-

-

ns

RST to STBY Falling

tdrrs

-

100

-

ns

RST Rising to STBY Rising

tcal

-

34,584,480

-

tclk

HOLD Pulse Width

thold 2tclk+50

-

192tclk ns

HOLD to L/R Edge

(Note 10) tdhlri

-30

-

192tclk ns

SCLK period

tsclk

200

-

-

ns

SCLK Pulse Width Low

tsclkl

50

-

-

ns

SCLK Pulse Width High

tsclkh

50

-

-

ns

SCLK Falling to SDATA Valid

tdss

-

100

140

ns

HOLD Falling to SDATA Valid

tdhs

-

140

200

ns

Notes: 10. SSH2 only works correctly if HOLD falling edge is within ±30ns of L/R edge OR if HOLD falling edge

occurs between 30ns before HOLD rises to 192 tclk after HOLD falls.

HOLD (i)

SSH2 (o)

TRKL (o)

TRKR (o)

tdfsh2

tdrsh tdfsh1

Control Output Timing

RST

trst

tcal

STBY

tdrrs

Reset and Calibration Timing

L/R

HOLD

tdhlri

thold

Channel Selection Timing

SCLK

SDATA

tsclkl tsclkh

tsclk

tdss

Serial Data Timing

HOLD

SDATA

tdhs

MSB

SCLK

Data Transmit Start Timing

4

DS32F1

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