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CS5516-ASZ

16/20-bit bridge transducer A/D conveter

Cirrus Logic 

CS5516, CS5520

SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 5%;

VA-, VD- = -5V±5%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF)

Parameter

Symbol Min

Typ

Max Units

Master Clock Frequency: Internal Oscillator / External Clock XIN

1.0

4.096

5.0

MHz

Master Clock Duty Cycle

40

-

60

%

Rise Times

Any Digital Input (Note 18) trise

-

Any Digital Output

-

-

1.0

µs

50

-

ns

Fall Times

Any Digital Input (Note 18) tfall

-

Any Digital Output

-

-

1.0

µs

50

-

ns

Startup

Power-on Reset Period

tpor

-

100

-

ms

Oscillator Start-up Time

XTAL = 4.9152 MHz(Note 19) tost

-

60

-

ms

RST Pulse Width

tres

1/XIN

-

-

ns

Serial Port Timing

Serial Clock Frequency

SCLK

-

-

2.4

MHz

Serial Clock

Pulse Width High

Pulse Width Low

t1

200

-

t2

200

-

-

ns

-

ns

SID Write Timing

CS Enable to Valid Latch Clock

t3

150

-

-

ns

Data Set-up Time prior to SCLK rising

t4

50

-

-

ns

Data Hold Time After SCLK Rising

t5

50

-

-

ns

SCLK Falling Prior to CS Disable

SOD Read Timing

t6

50

-

-

ns

CS to Data Valid

t7

-

-

150

ns

SCLK Falling to New Data Bit

t8

-

-

170

ns

SCLK Falling to SOD Hi-Z

t9

-

-

200

ns

DRDY Falling to Valid Data (CS = 0)

t10

-

-

150

ns

CS Rising to SOD Hi-Z

t11

-

-

150

ns

CS Disable Hold Time

t12

50

-

-

ns

CS Enable Set-up Time

t13

150

-

-

ns

CS Enable Hold Time

t14

50

-

-

ns

CS Disable Set-up Time

t15

150

-

-

ns

Notes: 18. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

19. Oscillator start-up time varies with crystal parameters. This specification does not apply when using

an external clock source.

DS74F21

9

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