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CS5525-BS Ver la hoja de datos (PDF) - Cirrus Logic

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CS5525-BS Datasheet PDF : 29 Pages
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CS5525
CS5526
16-Bit/20-Bit Multi-Range ADC with 4-Bit Latch
Features
Delta-Sigma A/D Converter
- Linearity Error: 0.0015%FS
- Noise Free Resolution: 18-bits
Bipolar/Unipolar Input Ranges
- 25 mV, 55 mV, 100 mV, 1 V, 2.5 V and 5 V
Chopper Stabilized Instrumentation Amplifier
On-Chip Charge Pump Drive Circuitry
4-Bit Output Latch
Simple three-wire serial interface
- SPI™ and Microwire™ Compatible
- Schmitt Trigger on Serial Clock (SCLK)
Programmable Output Word Rates
- 3.76 Hz to 202Hz (XIN = 32.768 kHz)
- 11.47 Hz to 616 Hz (XIN = 100 kHz)
Output Settles in One Conversion Cycle
Simultaneous 50/60 Hz Noise Rejection
System and Self-Calibration with
Read/Write Registers
Single +5 V Analog Supply
+3.0 V or +5 V Digital Supply
Low Power Mode Consumption: 4.9 mW
- 1.8 mW in 1 V, 2.5 V, and 5 V Input Ranges
General Description
The 16-bit CS5525 and the 20-bit CS5526 are highly in-
tegrated ∆Σ A/D converters which include an
instrumentation amplifier, a PGA (programmable gain
amplifier), eight digital filters, and self and system cali-
bration circuitry.
The converters are designed to provide their own nega-
tive supply which enables their on-chip instrumentation
amplifiers to measure bipolar ground-referenced signals
±100 mV. By directly supplying NBV with -2.5 V and
with VA+ at 5 V, ±2.5 V signals (with respect to ground)
can be measured.
The digital filters provide programmable output update
rates between 3.76 Hz to 202 Hz (XIN = 32.768 kHz).
Output word rates can be increased by approximately 3X
by using XIN = 100 kHz. Each filter is designed to settle
to full accuracy for its output update rate in one conver-
sion cycle. The filters with word rates of 15 Hz or less
(XIN = 32.768 kHz) reject both 50 and 60 Hz (±3 Hz) line
interference simultaneously.
Low power, single conversion settling time, programma-
ble output rates, and the ability to handle negative input
signals make these single supply products ideal solu-
tions for isolated and non-isolated applications.
ORDERING INFORMATION
See page26.
VA+
AGND
VREF+ VREF-
DGND
VD+
AIN+
AIN-
+
X20
-
Programmable
Gain
NBV
A0
A1
A2
A3
Latch
Calibration
Memory
Differential
4th Order
Delta-Sigma
Modulator
Digital Filter
Calibration µC
Clock
Gen.
Calibration
Register
Control
Register
Output
Register
CS
SCLK
SDI
SDO
Cirrus Logic, Inc.
www.cirrus.com
CPD
XIN XOUT
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
Nov ‘03
DS202F3
1

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