CS5511-AS(2000) Ver la hoja de datos (PDF) - Cirrus Logic
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CS5511-AS Datasheet PDF : 26 Pages
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CS5510/11/12/13
as great as (V+) - (V-). The VREF pin can be con-
nected directly to the V+ pin. This will establish a
voltage reference equal to (V+) - (V-) for the con-
verter. The effective resolution of the part (noise-
free bits for a single sample with no averaging) will
vary with VREF. Figure 4 shows how the VREF
voltage affects the noise-free resolution of the
CS5512/13. The CS5510/11 follow the same curve,
but are limited to 16 bits of resolution. Note that the
reference voltage should not be established prior to
having the supply voltages on the V+ and V- pins.
2.2.1 Voltage Reference Input Model
Figure 5 illustrates the input model for the VREF
pin. It includes a coarse/fine charge buffer which
reduces the dynamic current demand of the exter-
nal reference. Typical CVF (sampling) current is
about 6 nA (See Figure 5).
The nominal input span of the converter is defined
to be a bipolar span equal to ±(VREF - V-)*(0.80
±0.08).
2.3 Power Supply Arrangements
The CS5510/11/12/13 are designed to operate from
single or dual supplies. Figure 6 illustrates the
CS5510/11/12/13 connected with a single +5 V
supply to measure differential inputs relative to a
common mode of 2.5 V. Figure 7 illustrates the
CS5510/11/12/13 connected with ±2.5 V analog
supplies to measure ground referenced bipolar sig-
nals. It is not necessary that the dual supples on the
ADCs be balanced, however, they must sum to five
volts. Figure 8 illustrates the ADCs configured
with V+ = +3.3 V and V- = -1.7 V, accommodating
a +3.3 V digital supply.
17
16
15
14
13
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VREF (V)
Figure 4. CS5512/13 Measured Noise-Free Bits vs. VREF.
Effective Bits = Log2(Bipolar Span / 6.6*RMS Noise)
VREF
Vo s ≤ 2 5 mV
i n = f Vo s C
φ 1 Fine
φ2 Coarse
C = 7pF
f = 32.768 kHz
Figure 5. Input model for VREF pin.
DS337F1
11
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