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CS5510-AS
(Rev.:2000)

16 and 20-Bit, 8-Pin ∆Σ ADC

Cirrus Logic 

CS5510/11/12/13

2.5.5 Multiplexed Applications

The settling performance of the CS5510/11/12/13

in multiplexed applications is determined by the

Sinc4 filter. To settle a step input requires 4 full

conversion cycles after the analog input has

switched. In this case, the throughput is reduced by

a factor of four as the first three conversions after

the step is applied will not be fully settled.

If the application does not require the maximum

throughput possible from the ADC, the multiplexer

can be switched at any time. In this case, the system

must wait for at least five conversion cycles for a

fully-settled result from the ADC.

If maximum throughput is required in a multi-

plexed application, the multiplexer must be

switched at the correct time during the data collec-

tion process. For maximum throughput with the

CS5510/12, switching of a multiplexer should oc-

cur 595 SCLK cycles after SDO falls. For maxi-

mum throughput with the CS5511/13, switching of

a multiplexer should occur on the rising edge of

SDO during a conversion in which the data word is

not read. The conversion data that is immediately

available when SDO falls again is valid, and repre-

sents the analog input from the previous multiplex-

er setting. The next three conversions from the part

will be unsettled values, and the fourth conversion

will represent a fully-settled result from the new

multiplexer setting. The multiplexer should be

switched again at the appropriate time during the

third conversion cycle to ensure the maximum pos-

sible throughput.

2.6 Digital Off-Chip System Calibration

The CS5510/11/12/13 exhibit excellent linearity

with low offset and gain drift, without the need for

calibration. If precision voltage measurements are

required by the system, however, software-based

offset and gain calibration can be performed by the

system.

To perform a software offset calibration, the “zero-

point” of the system should be established by ap-

plying an input to the system equal to zero. Then,

the user can obtain a conversion and store it in

memory as the system’s zero point (ZP). This num-

ber can then be used as the zero point for any sub-

sequent conversion words. In the 20-bit devices

(CS5512 and CS5513), multiple conversions can

be averaged to arrive at a more accurate offset val-

ue. In the 16-bit devices (CS5510 and CS5511), av-

eraging may not be meaningful, because the noise

will be below the size of one LSB when using nom-

inal voltages for VREF (2.5 V).

A software gain calibration can be performed by

bringing the system to a known calibration Voltage

value (Vcal) and acquiring a conversion (note that

Vcal should be low enough to compensate for the

possible gain error of the ADC). Multiple conver-

sions can be averaged at this point to improve the

accuracy of the calibration. The code obtained from

this conversion is the real value (Cr) of the calibra-

tion Voltage input, and will differ from the ideal

value. The ideal value for this conversion (Ci) will

be equivalent to: 0x7FFF*Vcal/(0.80*Vref) for the

CS5510/11, and 0x7FFFF*Vcal/(0.80*Vref) for

the CS5512/13. The gain error (GE) is equal to: (Cr

- ZP)/Ci. To correct for both offset and gain error in

subsequent conversions, subtract the offset error,

and then divide by the gain error.

2.7 Power Consumption, Sleep and Reset

The CS5510/11/12/13 accommodates two power

consumption modes: normal and sleep. The normal

mode is the default mode and is entered after power

is established to the ADC. In normal mode, the

ADCs typically consumes 2.5 mW. Sleep is en-

tered when the user leaves SCLK high for at least

200 µs. The ADCs are guaranteed to be in sleep af-

ter SCLK is high (logic 1) for 2 ms. The sleep mode

reduces the consumed power to less than 10 µW

when CS is high (logic 1). If CS is low (logic 0) at

this time, the SDO drive logic will still be active,

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DS337F1

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