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CS5512(2000) Ver la hoja de datos (PDF) - Cirrus Logic

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Lista de partido
CS5512
(Rev.:2000)
Cirrus-Logic
Cirrus Logic Cirrus-Logic
CS5512 Datasheet PDF : 26 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
CS5510/11/12/13
ANALOG CHARACTERISTICS (Continued)
Parameter
Voltage Reference Input
Range
{(VREF) - (V-)}
Input Capacitance
CVF current
Power Supplies
Supply Voltages
{(V+) - (V-)}
DC Power Supply Currents
IV+
IV-
Power Consumption
Power Supply Rejection
Sleep
dc Positive Supply
dc Negative Supply
Min
Typ
Max
Unit
(Note 8) 0.250
2.5
(V+) - (V-) V
-
7
-
pF
-
6
-
nA
4.75
5
(Note 9)
CS5510 -
275
CS5511 -
290
CS5512 -
360
CS5513 -
385
CS5510 -
275
CS5511 -
290
CS5512 -
360
CS5513 -
385
(Note 10)
CS5510 -
1.4
CS5511 -
1.5
CS5512 -
1.8
CS5513 -
1.9
(Note 11) -
10
-
85
-
85
5.25
V
360
µA
380
µA
470
µA
500
µA
360
µA
380
µA
470
µA
500
µA
1.9
mW
2.0
mW
2.5
mW
2.7
mW
-
µW
-
dB
-
dB
Notes: 8. VREF is referenced to V- and must be less than or equal to V+.
9. Due to current through the CS pin, IV+ and IV- may not always be the same value.
10. All outputs unloaded. All inputs CMOS levels (> (V+ - 0.6 V) or < (V- + 0.6 V)).
11. CS must be inactive (logic high) during sleep to meet this power specification.
DIGITAL CHARACTERISTICS (TA = 25° C; V+ = 5 V ±5%; V- = 0 V) (See Notes 1 and 12.)
Parameter
Symbol Min Typ
Max
Unit
High-Level Input Voltage:
Low-Level Input Voltage:
Input Current:
High-Level Output Voltage:
Low-Level Output Voltage:
Input Leakage Current
3-State Leakage Current
CS and SCLK VIH V+ - 0.45 -
-
V
(Note 13) CS CSLow
-
-
SCLK VIL
-
-
(Note 14) CS ICS
-
-
SDO, Isource = 5.0mA VOH (V+) - 0.6 -
VL1
V
VL1
V
1.0
mA
-
V
(Note 14) SDO, Isink = 1.0mA VOL
-
- (CSLow) + 0.6 V
SCLK Iin
- ±0.015
±10
µA
SCLK IOZ
-
-
±10
µA
Notes: 12. All measurements performed under static conditions.
13. VL1 is 0.5 (V+ - V-) + 0.6 V + V-.
14. The CS signal provides the sink current path for the SDO pin when CS is low. The external drive logic
to CS, therefore, must be able to handle the logic-low current drive levels for all devices attached to
SDO. The voltage specified for SDO is relative to CSLow. See Section 2.3.1, “Digital Logic Levels” and
Figure 11 for more details.
DS337F1
5

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