MSM6779 Ver la hoja de datos (PDF) - Oki Electric Industry

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Lista de partido

MSM6779

160-DOT SEGMENT DRIVER (TCP)

Oki Electric Industry 

¡ Semiconductor

PEDL6779B-01

MSM6779B

FUNCTIONAL DESCRIPTION

Pin Descriptions

VDD, VSS

Power supply for the device. VDD is set to 2.7 V to 5.5 V. VSS is set to 0 V.

V1L, V1R, V3L, V3R, V4L, V4R, VEEL, VEER

Bias power supply for the LCD drive voltages. Power supply should be

VDD≥V1>V3>V4>VEE.

DISPOFF

Input for controlling the output level of O1 to O160. The V1 level is output from O1 to O160 pins

during "L" level input. Refer to Truth Table.

DF

Input for LCD drive wave form AC synchronization.

O1~O160

LCD drive outputs that correspond to each bit of the latch (II). Depending on the combination

of the contents of the latch (display data) and DF signal, one of 4 levels (V1, V3, V4, VEE) is output.

Refer to Truth Table.

CP

Clock pulse input for display data reading. Data is taken into the latch (I) at the falling edge of

the clock pulse.

Use an even number for the clock number per line (the number of the clock pulses during the

period from Load input to the next Load input).

EIO1, EIO2

Chip Select Signal Input/Output. Input/Output are controlled by the SHL input. If the SHL

input at "L"level,EIO1 is output and EIO2 is input. If the SHL input is at "H" level,EIO1 is input

and EIO2 is output. If the SHL is at "L" level, the first EIO2 is fixed to "L"level,and the following

EIO2 is connected to the preceding EIO1. If the SHL is at "H"level,the first EIO1 is fixed to "L" level,

and the following EIO1 is connected to the preceding EIO2 as shown below.

When SHL is at "L" level

Start data

O160

EIO2

EIO1

EIO2

EIO1

End data

O1

EIO2

When SHL is at "H" level

End data

O160

EIO1

EIO2

EIO1

Start data

O1

EIO2

EIO1

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