V54C316162V-5 Ver la hoja de datos (PDF) - Mosel Vitelic, Corp

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V54C316162V-5

200/183/166/143 MHz 3.3 VOLT/ 4K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16

Mosel Vitelic, Corp 

MOSEL VITELIC

Read and Write Operation

When RAS is low and both CAS and WE are high

at the positive edge of the clock, a RAS cycle starts.

According to address data, a word line of the select-

ed bank is activated and all of sense amplifiers as-

sociated to the wordline are set. A CAS cycle is

triggered by setting RAS high and CAS low at a

clock timing after a necessary delay, tRCD, from the

RAS timing. WE is used to define either a read

(WE = H) or a write (WE = L) at this stage.

SDRAM provides a wide variety of fast access

modes. In a single CAS cycle, serial data read or

write operations are allowed at up to a 166 MHz

data rate. The numbers of serial data bits are the

burst length programmed at the mode set operation,

i.e., one of 1, 2, 4, 8 and full page. Column address-

es are segmented by the burst length and serial

data accesses are done within this boundary. The

first column address to be accessed is supplied at

the CAS timing and the subsequent addresses are

generated automatically by the programmed burst

length and its sequence. For example, in a burst

length of 8 with interleave sequence, if the first ad-

dress is ‘2’, then the rest of the burst sequence is 3,

0, 1, 6, 7, 4, and 5.

Full page burst operation is only possible using

the sequential burst type and page length is a func-

tion of the I/O organisation and column addressing.

Full page burst operation do not self terminate once

the burst length has been reached. In other words,

unlike burst length of 2, 4 or 8, full page burst con-

tinues until it is terminated using another command.

V54C316162V

Similar to the page mode of conventional

DRAM’s, burst read or write accesses on any col-

umn address are possible once the RAS cycle

latches the sense amplifiers. The maximum tRAS or

the refresh interval time limits the number of random

column accesses. A new burst access can be done

even before the previous burst ends. The interrupt

operation at every clock cycles is supported. When

the previous burst is interrupted, the remaining ad-

dresses are overridden by the new address with the

full burst length. An interrupt which accompanies

with an operation change from a read to a write is

possible by exploiting DQM to avoid bus contention.

When two or more banks are activated

sequentially, interleaved bank read or write

operations are possible. With the programmed

burst length, alternate access and precharge

operations on two or more banks can realize fast

serial data access modes among many different

pages. Once two or more banks are activated,

column to column interleave operation can be done

between different pages.

Refresh Mode

SDRAM has two refresh modes, Auto Refresh

and Self Refresh. Auto Refresh is similar to the CAS

-before-RAS refresh of conventional DRAMs. All of

banks must be precharged before applying any re-

fresh mode. An on-chip address counter increments

the word and the bank addresses and no bank infor-

mation is required for both refresh modes.

Burst Length and Sequence:

Burst Starting Address Sequential Burst Addressing

Length

(A2 A1 A0)

(decimal)

2

xx0

0, 1

xx1

1, 0

4

x00

x01

x10

x11

0, 1, 2, 3

1, 2, 3, 0

2, 3, 0, 1

3, 0, 1, 2

8

000

001

010

011

100

101

110

111

01234567

12345670

23456701

34567012

45670123

56701234

67012345

70123456

Full

nnn

Page

Cn, Cn+1, Cn+2,.....

Interleave Burst Addressing

(decimal)

0, 1

1, 0

0, 1, 2, 3

1, 0, 3, 2

2, 3, 0, 1

3, 2, 1, 0

01234567

10325476

23016745

32107654

45670123

54761032

67452301

76543210

not supported

V54C316162V Rev. 2.9 September 2001

6

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