CS48LV12CWZR Ver la hoja de datos (PDF) - Cirrus Logic

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CS48LV12CWZR

Ultralow Power HD Voice Processors, Featuring SoundClear® Technology

Cirrus Logic 

4.7 Switching Characteristics—RESET

4.7 Switching Characteristics—RESET

Parameter

Symbol

Min

Max

RESET minimum pulse width low1

All bidirectional pins high-Z after RESET low

Configuration pins setup before RESET high

Configuration pins hold after RESET high

Trstl

1

—

Trst2z

—

100

Trstsu

50

—

Trsthld

20

—

1.The rising edge of RESET must not occur before the power supplies are stable at their recommended operating values. In addition, for the

configuration pins to be read correctly, the RESET Trstl requirement must be met.

Unit

s

ns

ns

ns

VD,

VPLL,

VL

RESET

All supplies at

recommended

operating values.

Trstl

INT

BUSY/I2C_SELECT

Trstsu Trsthld

Figure 4-2. RESET Timing at Power-On

RESET

INT

BUSY/I2C_SELECT

All Bidirectional

Pins

Trst2z

Trstl

T rstsu Trsthld

Figure 4-3. RESET Timing after Power is Stable

4.8 Switching Characteristics—CLOCK

Parameter

External clock operating frequency

CLOCK period

CLOCK high time

CLOCK low time

CLOCK

Symbol

FCLOCK

TCLOCK

TCLOCKh

TCLOCKl

Min

3.072

26

45% · TCLOCK

45% · TCLOCK

tCLOCKh

TCLOCK

t CLOCKl

Figure 4-4. CLOCK Timing

Max

38.4

325

55% · TCLOCK

55% · TCLOCK

Unit

MHz

ns

ns

ns

DS1057F1

16

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