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CS48LV13-CNZR Datasheet PDF : 26 Pages
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4.9 Switching Characteristics—Internal Clock
4.9 Switching Characteristics—Internal Clock
Parameter
Internal DCLK frequency1 (VD, VPLL = 1.2 V)
Internal DCLK frequency1 (VD, VPLL = 1.0 V)
Internal DCLK period (VD, VPLL = 1.2 V)
Internal DCLK period (VD, VPLL = 1.0 V)
Cycle-to-cycle jitter on Internal DCLK or Mastered MCLK2
Symbol
Fdclk
Fdclk
DCLKP
DCLKP
—
Min
FCLOCK/256
FCLOCK/256
7.69
12.5
—
Typ
Max
Unit
—
130
MHz
—
80
MHz
—
256/FCLOCK
ns
—
256/FCLOCK
ns
500
—
ps
1.After initial power-on reset, Fdclk = FCLOCK. After initial kick-start commands, the PLL is locked to max Fdclk and remains locked until PLL is
reconfigured for a new setting or the next RESET pulse.
2.This parameter is characterized with a VCO speed of 330 MHz.
4.10 Switching Characteristics—Serial Control Port—SPI Slave Mode
Parameter
Symbol
Min
Typical
Max
Units
CLK frequency1
CS falling to CLK rising
CLK low time
CLK high time
Setup time MOSI input
Hold time MOSI input
CLK low to MISO output valid
CLK falling to INT rising
CS rising to INT falling
CLK low to CS rising
CS rising to MISO output high-Z
CLK rising to BUSY falling
fspisck
—
—
tspicss
24
—
tspickl
20
—
tspickh
20
—
tspidsu
5
—
tspidh
5
—
tspidov
—
—
tspiirqh
—
—
tspiirql
0
—
tspicsh
24
—
tspicsdz
—
20
tspicbsyl
—
3*DCLKP+20
25
MHz
—
ns
—
ns
—
ns
—
ns
—
ns
11
ns
20
ns
—
ns
—
ns
—
ns
—
ns
1.The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the
communication port can be limited by the firmware application. Flow control using the BUSY pin should be implemented to prevent overflow of the
input data buffer. Maximum SPI clock speed is Fdclk/2. Before locking PLL, Fdclk = FCLOCK.
17
DS1057F1
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